EP910DC-35 vs EP910DC-15 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910DC-35 disebabkan oleh Altera dan EP910DC-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910DC-35 | EP910DC-15 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Device Type | UV-Erasable CMOS PLD (PAL-type) | — |
| Family | Classic EPLD EP910 | Altera Classic EPLD |
| Architecture | PAL-type sum-of-products AND-OR array | — |
| Usable Gates | 900 gates | — |
| Macrocells | 24 | 24 |
| Product Terms | 240 | — |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | — |
| Total Inputs | 36 | — |
| Propagation Delay (tpd) | 35 ns | — |
| Frekuensi Klock Maksimum | 37 MHz (typical, internal) | — |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V (5 V nominal) | — |
| Suhu Operasi | 0 °C to +70 °C (commercial) | 0C to +70C (commercial) |
| Kemasan | 40-pin CDIP (Ceramic DIP) with quartz window | 24-pin ceramic DIP (DC) |
| Lead Pitch | 2.540 mm | — |
| Termination Style | Through-Hole | — |
| Programming Method | JEDEC fuse map via device programmer; UV erase | — |
| Technology | CMOS, UV-erasable EPROM cell | CMOS EPROM, UV-erasable |
| Status RoHS | Non-compliant (ceramic DIP with Pb-bearing lead finish) | [DATA_NEEDED: not explicitly stated in verified data] |
| Lifecycle | Obsolete / last-time-buy from authorized distributors | — |
| Device Density | — | 900 usable gates |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Bidirectional I/O Pins | — | 12 |
| Flip-Flops | — | 10 |
| Product Terms per Macrocells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Speed Grade | — | 15 |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Jenis Pemasangan | — | Through-Hole |
| Aras MSL | — | [DATA_NEEDED: MSL level] |