EP910IDC-15 vs EP910DC-30 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910IDC-15 disebabkan oleh Altera dan EP910DC-30 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910IDC-15 | EP910DC-30 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Manufacturer | Altera (now Intel PSG) | — |
| Family | Classic EPLD | Classic EPLD (EP910 series) |
| Equivalent Gates | 450 | — |
| Macrocells | 24 | 24 |
| Flip-Flops | 48 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Maximum Frequency (fCNT) | 66.6 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Kemasan | 40-pin CDIP (Ceramic DIP, through-hole) | DIP-40 (through-hole, 600 mil) |
| Terminal Count | 40 | — |
| Terminal Form | Through-Hole | — |
| Temperature Grade | Commercial (0C to +70C) | — |
| Programmable Security Bit | Yes | — |
| On-board Test Circuitry | Yes | — |
| Logic Type | UV Erasable EPROM-based | — |
| I/O Pins | 24 | — |
| Dedicated Inputs | 10 | 36 |
| Programming Technology | EPROM (UV-erasable) | — |
| Status RoHS | non_compliant (ceramic DIP contains lead) | — |
| Architecture | — | PAL-type AND-OR sum-of-products, CMOS |
| Gate Count | — | 900 usable gates |
| Propagation Delay (tPD) | — | 30 ns (max) |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| Tegangan Pemberi Arus | — | 5 V |
| Process Technology | — | CMOS |
| Programming Method | — | UV-Erasable / OTP |
| Suhu Operasi | — | 0C to +70C (commercial) |
| Jenis Pemasangan | — | Through-Hole |