EP910PC-30 vs EP910PI-12T Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910PC-30 disebabkan oleh Altera dan EP910PI-12T disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910PC-30 | EP910PI-12T |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | ~450 | — |
| Pin-to-Pin Propagation Delay (tPD) | 30 ns | — |
| Maximum Counter Frequency (fCNT) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V ±10% | 5 V (4.75 V min, 5.25 V max) |
| Logic Inputs | 36 dedicated | — |
| I/O Pins | 12 bidirectional | 24 |
| Logic Array Blocks (LABs) | 4 | — |
| Kemasan | PDIP-40 (plastic DIP, 0.6 inch) | 40-pin PDIP (Plastic DIP) |
| Suhu Operasi | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Technology | UV-erasable EPROM cell | — |
| TTL Emulation | 100% TTL-compatible | — |
| Power Dissipation | [DATA_NEEDED: power dissipation mW] | — |
| Status RoHS | Non-compliant (contains lead, PDIP package) | Non-compliant (legacy PDIP package, contains lead) |
| Jenis Pemasangan | Through-hole DIP | — |
| Propagation Delay (tPD) | — | 12 ns |
| Maximum Operating Frequency | — | 76.9 MHz |
| Logic Gates | — | [DATA_NEEDED: logic gate count] |
| Dedicated Inputs | — | 12 |
| External Clock Inputs | — | 2 |
| Outputs | — | 24 |
| Terminals / Pin Count | — | 44 (PDIP-40 package pinout with NC pins) |
| Process Technology | — | CMOS |
| Programmable Technology | — | UV-erasable EPROM |
| Programming Interface | — | JEDEC-standard |
| Status Lingkungan Hidup | — | NRND / EOL (mature legacy product) |