EPC16UC80 vs EPC16UC88 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPC16UC80 disebabkan oleh Altera dan EPC16UC88 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPC16UC80 - 16Mb Enhanced Config Device, 80-pin UBGA | Altera
EPC16UC80 ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EPC16UC80 | EPC16UC88 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | Memory ICs | Memory ICs |
| Status Lingkungan Hidup | Masa Terakhir Dibeli | Unknown |
| Memory Density | 16 Mbit | — |
| Device Family | EPC4 / EPC8 / EPC16 Enhanced Configuration Device | — |
| Configuration Memory Sections | 8 (multi-boot capable) | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (typical 3.3 V) | — |
| Configuration Clock (DCLK) | Up to 33 MHz (FPP mode) | — |
| Configuration Modes | FPP, PS, JTAG | — |
| Antaramuka | Parallel data + DCLK + nSTATUS + nCONFIG + CONFIG_DONE | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | IEEE Std. 1532 compatible |
| Endurance | 100,000 erase/program cycles (per datasheet) | — |
| Suhu Operasi | -40 C to +85 C (industrial) | [DATA_NEEDED: operating temperature] |
| Kemasan | 80-ball UBGA (Ultra FineLine BGA), 11x8 mm | 88-UBGA (11x8) |
| Jenis Pemasangan | Surface Mount | Surface mount |
| Supported Target FPGAs | Stratix/II/III/GX, Cyclone/II/III, APEX 20K/II/IIE, Mercury | — |
| Lead-Free / RoHS | Compliant per Altera product page | — |
| Multi-Device Daisy-Chain | Yes | — |
| Device Type | — | In-system programmable configuration PROM for FPGAs |
| Configuration Memory Capacity | — | 16 Mb |
| Tegangan Pemberi Arus | — | 3.3 V core and I/O |
| Package Family | — | UBGA |
| Programming Language Support | — | Jam Standard Test and Programming Language (STAPL) |
| JTAG Boundary Scan | — | Supported |
| nINIT_CONF Function | — | Allows private JTAG instruction to start FPGA configuration |
| Configuration Architecture | — | Configuration controller and flash memory |
| FPGA Configuration Use | — | Automatic configuration after power-up or system initialization |
| Data Output | — | Configuration data output controlled by OE and nCS |
| Output Control | — | OE and nCS control tri-state buffer and address counter |
| Package Dimensions | — | 11 mm x 8 mm |
| Status RoHS | — | [DATA_NEEDED: RoHS status] |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| Output Current | — | [DATA_NEEDED: output current] |
| Configuration Frequency | — | [DATA_NEEDED: configuration frequency] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |