EPC1TI32 vs EPC2-TC32 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPC1TI32 disebabkan oleh Altera dan EPC2-TC32 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Intel
EPC2-TC32 - 1.6Mb ISP Configuration PROM | Altera | TQFP-32
EPC2-TC32 ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EPC1TI32 | EPC2-TC32 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | Memory ICs | Memory ICs |
| Status Lingkungan Hidup | Obsolete | Masa Terakhir Dibeli |
| Jenis Ingatan | FPGA Configuration PROM (Serial, OTP) | EPROM (OTP/UV-erasable configuration PROM) |
| Memory Density | 1 Mbit (1,046,496 bits) | — |
| Antaramuka | Altera 4-pin serial (DCLK, DATA, nCONFIG, nSTATUS) | — |
| Programming Interface | JTAG (IEEE 1149.1) | — |
| Tegangan Pemberi Arus | 3.3 V (derived from VCCIO of target FPGA) | 3.3 V |
| Kemasan | 32-pin TQFP (7 x 7 mm) | 32-pin TQFP (7x7 mm) |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Suhu Operasi | -40 C to +85 C (industrial) | — |
| Compatible FPGAs | ACEX 1K, FLEX 10K, FLEX 6000, MAX 9000 | — |
| Replacement For | EPC1064, EPC1441 | — |
| Configuration Software | Quartus II, MAX+PLUS II | — |
| Programming Hardware | MasterBlaster / ByteBlasterMV / USB-Blaster | — |
| Status RoHS | [DATA_NEEDED: rohs status from datasheet] | [DATA_NEEDED: RoHS status - datasheet does not specify in retrieved snippet] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Aras MSL | [DATA_NEEDED: MSL level] | MSL 3 (168 hours) |
| Saiz Ingatan | — | 1.6 Mbit |
| Jenis Antaramuka | — | Serial |
| Organisasi | — | Serial bitstream output |
| Programmability | — | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| Gambaran Suhu Operasi | — | 0C to +70C (Commercial) |
| Supported FPGA Families | — | Stratix I/II, Cyclone I/II, APEX 20K/II, Mercury, ACEX 1K, FLEX 10K |
| Configuration Mode | — | Serial (FPP/MSD via FPGA master/slave) |
| Output Control | — | OE and nCS gating internal tri-state buffer |
| Internal Oscillator | — | Yes (drives address counter) |