EPF10K30EFC256-2XN vs EPF10K30EFC256-3N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPF10K30EFC256-2XN disebabkan oleh Altera dan EPF10K30EFC256-3N disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPF10K30EFC256-2XN - 30K FLEX-10KE FPGA, 256-BGA, Industrial | Altera
EPF10K30EFC256-2XN ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EPF10K30EFC256-2XN | EPF10K30EFC256-3N |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Masa Terakhir Dibeli | Obsolete |
| Family | FLEX 10KE | FLEX 10KE |
| Typical Gates | 30,000 | — |
| Logic Elements | 1,728 | — |
| Logic Cells | 1,728 | — |
| Embedded RAM Bits | 24,576 (6 x 4,096-bit EABs) | — |
| User I/O Pins | 176 | — |
| Logic Blocks (LABs) | 216 | — |
| Process Technology | 0.22 micrometer CMOS, 4-layer metal | 0.22 um CMOS |
| Core Supply Voltage | 2.5 V (2.375 V to 2.625 V) | — |
| Internal Frequency (max) | 200 MHz | — |
| Speed Grade | -2 | — |
| I/O Standards Supported | 3.3 V, 5.0 V (MultiVolt I/O) | — |
| Suhu Operasi | -40 C to +85 C (Industrial, 'N' suffix) | 0 C to +70 C (Commercial) |
| Kemasan | 256-ball FBGA, 17x17 mm | 256-pin FineLine BGA (FBGA) |
| Configuration Interface | JTAG / serial via EPC EEPROM | — |
| Jenis Pemasangan | Surface Mount | — |
| Lead-Free / RoHS | Yes (per 'N' suffix) | — |
| Aras MSL | 3 (168 hours) | — |
| Logic Elements / Cells | — | 1,728 |
| Gate Count | — | 30,000 gates |
| Logic Array Blocks (LABs) | — | 216 |
| Embedded Array Blocks (EABs) | — | 6 |
| Embedded RAM | — | 24,576 bits |
| Maximum User I/Os | — | 176 |
| Core Voltage | — | 2.5 V |
| I/O Standard Support | — | MultiVolt 2.5 V / 3.3 V / 5.0 V |
| Internal Frequency | — | 80 MHz (typical) |
| Propagation Delay (tPD) | — | 0.6 ns |
| Bidirectional I/O Performance | — | up to 212 MHz |
| PCI Compliance | — | PCI SIG 2.2 at 33 / 66 MHz |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Open-Drain I/O Option | — | Yes (per pin) |