EPM3064ATC44-10N vs EPM3064ATC44-10 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3064ATC44-10N disebabkan oleh Altera dan EPM3064ATC44-10 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM3064ATC44-10N EPM3064ATC44-10
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Aktif Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Usable Gates 1250 1,250
Macro Cells 64 —
User I/O Pins 34 —
Logic Array Blocks (LABs) 4 —
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Counter Frequency 192.3 MHz —
Supply Voltage (VCCINT) 3.3 V 3.0 V to 3.6 V (3.3 V typical)
I/O Standard MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V) —
Configuration Memory EEPROM (non-volatile) —
In-System Programming IEEE Std. 1532 compliant IEEE Std. 1532 (JTAG)
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) compliant —
Kemasan TQFP-44 (10x10 mm) TQFP-44, 10 x 10 mm, 0.8 mm pitch
Jenis Pemasangan Surface Mount Surface Mount
Suhu Operasi 0C to +70C (commercial) —
Status RoHS Compliant Non-compliant (legacy Altera, Pb-bearing)
Pin-Locking Yes (across design iterations) —
Logic Elements / Macrocells — 64 macrocells
Number of Logic Blocks / LABs — 4 LABs
Propagation Delay (tPD) — 10 ns
Maximum Internal Frequency — 227.3 MHz (counter speed)
Programmable I/Os — 34
I/O Bank Voltage (VCCIO) — MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V
Technology — CMOS EEPROM, 5 V tolerant I/O
Boundary-Scan Support — IEEE 1149.1 (JTAG)
Gambaran Suhu Operasi — 0C to +70C (commercial)

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