EPM3064ATC44-7N vs EPM3064ATC44-10 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3064ATC44-7N disebabkan oleh Altera dan EPM3064ATC44-10 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM3064ATC44-7N EPM3064ATC44-10
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 64 —
Logic Array Blocks 2 —
Usable Gates 1,250 1,250
User I/O Pins 34 —
Bilangan Pin 44 —
Speed Grade -7 (7.5 ns pin-to-pin delay) —
Pin-to-Pin Delay (tPD) 7.5 ns —
Maximum Counter Frequency 192.3 MHz (-7 grade) —
Supply Voltage (VCC) 3.3 V —
MultiVolt I/O 1.8 V / 2.5 V / 3.3 V —
Programmability EEPROM, in-system programmable (ISP) —
JTAG Interface IEEE Std. 1149.1 compliant —
ISP Standard IEEE Std. 1532 compliant —
Boundary-Scan Test (BST) Built-in, JTAG-driven —
Kemasan 44-pin TQFP TQFP-44, 10 x 10 mm, 0.8 mm pitch
Suhu Operasi 0°C to +85°C (commercial) —
Jenis Pemasangan Surface Mount Surface Mount
Status RoHS Compliant Non-compliant (legacy Altera, Pb-bearing)
Logic Elements / Macrocells — 64 macrocells
Number of Logic Blocks / LABs — 4 LABs
Propagation Delay (tPD) — 10 ns
Maximum Internal Frequency — 227.3 MHz (counter speed)
Programmable I/Os — 34
Supply Voltage (VCCINT) — 3.0 V to 3.6 V (3.3 V typical)
I/O Bank Voltage (VCCIO) — MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V
Technology — CMOS EEPROM, 5 V tolerant I/O
In-System Programming — IEEE Std. 1532 (JTAG)
Boundary-Scan Support — IEEE 1149.1 (JTAG)
Gambaran Suhu Operasi — 0C to +70C (commercial)

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