EPM3256ATC144-10N vs EPM3256ATC144-10AA Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3256ATC144-10N disebabkan oleh Altera dan EPM3256ATC144-10AA disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N ⚠ Bahagian terakhir untuk beliAltera
EPM3256ATC144-10AA - MAX 3000A CPLD, 256 Macrocells, 10ns TQFP-144 | Altera
EPM3256ATC144-10AA ObsoletePengandingan Spesifikasi
| Parametr | EPM3256ATC144-10N | EPM3256ATC144-10AA |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Masa Terakhir Dibeli | Obsolete |
| Series | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macro Cells | 256 | — |
| Usable Gates | 5,000 (up to 10,000 usable in family) | 5,000 |
| Number of I/Os | 116 | — |
| Number of Logic Elements / Blocks | 16 LABs | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Propagation Delay (tPD) | 10 ns | 10 ns |
| Maximum Counter Frequency | 227.3 MHz | — |
| Global Clocks | 3 | — |
| Global Clear / OE | Yes (1 global clear, 1 global OE) | — |
| Program Memory Type | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Support | IEEE Std. 1149.1 with pin-locking | — |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | — |
| Kemasan | 144-LQFP (TQFP, ATC suffix) | 144-pin TQFP |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Suhu Operasi | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] | 0C to +70C (Commercial) |
| Status RoHS | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] | [DATA_NEEDED: RoHS status] |
| Lead-Free / Halogen-Free | [DATA_NEEDED: not explicitly confirmed in verified data] | — |
| Family | — | MAX 3000A |
| Macrocells | — | 256 |
| User I/O Pins | — | 116 |
| Maximum Operating Frequency | — | 95.2 MHz |
| Core Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V |
| Technology | — | CMOS, EEPROM-based configuration |
| In-System Programming | — | IEEE Std. 1532 compliant |