EPM3512AFC256-5C vs EPM3512AFC256C Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3512AFC256-5C disebabkan oleh Altera dan EPM3512AFC256C disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM3512AFC256-5C - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-5C ObsoleteIntel
EPM3512AFC256C - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera
EPM3512AFC256C ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EPM3512AFC256-5C | EPM3512AFC256C |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Masa Terakhir Dibeli |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | — |
| Maximum Operating Frequency | 95.2 MHz | — |
| Pin-to-Pin Delay (tPD) | 5 ns | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O) | — |
| User I/O Pins | 212 (max) | — |
| Kemasan | 256-ball FBGA, 17 mm × 17 mm, 1.0 mm pitch | 256-ball FineLine BGA (FC) |
| Suhu Operasi | 0 °C to +70 °C (commercial, "C" grade) | 0C to +70C (Commercial) |
| Programming Interface | IEEE Std. 1532 / JTAG (4-wire) in-system programmable | — |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Technology | EEPROM-based macrocell, non-volatile | — |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/Os | — | 208 |
| Dedicated Input Pins | — | 12 |
| Speed Grade | — | C (per datasheet ordering code) |
| Configuration Technology | — | EEPROM (non-volatile, instant-on) |
| Core Voltage | — | 3.3 V |
| I/O Standards Supported | — | MultiVolt: 5.0 V, 3.3 V, 2.5 V |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |
| PCI Compliance | — | PCI SIG Local Bus Specification Revision 2.2 |
| Programming | — | In-system programmable via JTAG |