EPM3512AFC256-7N vs EPM3512AFC256-2 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3512AFC256-7N disebabkan oleh Altera dan EPM3512AFC256-2 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM3512AFC256-7N - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera
EPM3512AFC256-7N ObsoletePengandingan Spesifikasi
| Parametr | EPM3512AFC256-7N | EPM3512AFC256-2 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | — |
| User I/Os | 208 | — |
| Logic Blocks | 16 (32 macrocells each) | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Internal Frequency (fMAX) | 116.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| 5V Tolerant I/O | Yes | — |
| In-System Programmability | IEEE Std. 1532 compliant | — |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE Std 1149.1) / ByteBlaster |
| Process Technology | CMOS EEPROM, 0.30 um | 0.30 um CMOS EEPROM |
| Kemasan | 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch | BGA-256 (FineLine BGA) |
| Suhu Operasi | 0 C to 70 C (commercial) | 0C to +70C (commercial) |
| Jenis Pemasangan | Surface Mount | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 212 |
| Propagation Delay (tPD, -2 grade) | — | [DATA_NEEDED: tPD ns] |
| Maximum Operating Frequency | — | [DATA_NEEDED: fMAX MHz] |
| Core Supply Voltage | — | 3.3 V |
| I/O Output Drive Voltage | — | 2.5 V or 3.3 V (MultiVolt) |
| Input Tolerance | — | 2.5 V, 3.3 V, 5.0 V tolerant |
| Ball Pitch | — | 1.0 mm |
| Speed Grade | — | -2 |