EPM3512AFI256-10N vs EPM3512AFC256C Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3512AFI256-10N disebabkan oleh Altera dan EPM3512AFC256C disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera
EPM3512AFI256-10N ⚠ Bahagian terakhir untuk beliIntel
EPM3512AFC256C - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera
EPM3512AFC256C ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EPM3512AFI256-10N | EPM3512AFC256C |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Masa Terakhir Dibeli | Masa Terakhir Dibeli |
| Family | MAX 3000A | MAX 3000A |
| Series | EPM3512 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | CMOS EEPROM-based, MAX architecture | — |
| Number of Macrocells | 512 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | Up to 10,000 | — |
| Number of User I/O | 208 | — |
| Total Pins | 256 | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | — |
| I/O Supply Voltage (VCCIO) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| MultiVolt I/O Support | 5.0 V / 3.3 V / 2.5 V | — |
| In-System Programmability | Yes - IEEE Std 1532 compliant | — |
| JTAG Boundary Scan | Yes - IEEE 1149.1 | — |
| Program Memory | EEPROM (non-volatile) | — |
| Kemasan | 256-ball FineLine BGA (FBGA-256) | 256-ball FineLine BGA (FC) |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Gambaran Suhu Operasi | -40 °C to +85 °C (industrial) | — |
| Status RoHS | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Speed Grade | -10 (10 ns tPD) | C (per datasheet ordering code) |
| Macrocells | — | 512 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/Os | — | 208 |
| Dedicated Input Pins | — | 12 |
| Suhu Operasi | — | 0C to +70C (Commercial) |
| Configuration Technology | — | EEPROM (non-volatile, instant-on) |
| Core Voltage | — | 3.3 V |
| I/O Standards Supported | — | MultiVolt: 5.0 V, 3.3 V, 2.5 V |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |
| PCI Compliance | — | PCI SIG Local Bus Specification Revision 2.2 |
| Programming | — | In-system programmable via JTAG |