EPM3512AQC208-10-10N vs EPM3256AQC208-10N Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3512AQC208-10-10N disebabkan oleh Altera dan EPM3256AQC208-10N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM3512AQC208-10-10N EPM3256AQC208-10N
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 3000A —
Macrocells 512 —
Usable Gates 10,000 10,000
User I/Os 172 —
Logic Elements / LABs 16 Logic Array Blocks —
Propagation Delay (tPD) 10 ns (-10 speed grade) —
Maximum Frequency (fCNT) 87 MHz —
Supply Voltage - Core (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V —
Process Technology CMOS EEPROM —
In-System Programmability Yes, IEEE Std. 1532 compliant —
Boundary-Scan (JTAG) Yes, IEEE 1149.1 —
PCI-SIG Compliance PCI Local Bus Specification Rev 2.2 (at -10 speed grade) —
Suhu Operasi 0 °C to +70 °C (commercial) 0C to +70C (Commercial)
Kemasan 208-pin PQFP (Plastic Quad Flat Pack) —
Jenis Pemasangan Surface Mount Surface Mount
Lead-Free / RoHS [DATA_NEEDED: RoHS status] —
Series — MAX 3000A
Programmable Type — In-System Programmable (EEPROM)
Number of Macrocells — 256
Number of Logic Elements/Blocks — 16 LABs
Number of I/O Pins — 161 (158 user I/O per Arrow listing)
Propagation Delay (tpd) — 10 ns (max)
Maximum Counter Frequency — 227.3 MHz
Supply Voltage - Internal — 3.0 V to 3.6 V (3.3 V typical)
Kemasan / Case — 208-BFQFP / 208-PQFP (28x28 mm)
ISP Compliance — IEEE Std. 1532
Boundary Scan — IEEE Std. 1149.1 (JTAG)
I/O Tolerance — 5 V tolerant, MultiVolt interface
Status RoHS — [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data]

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