EPM3512AQC208-10NS vs EPM3512AQC208-10N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3512AQC208-10NS disebabkan oleh Altera dan EPM3512AQC208-10N disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM3512AQC208-10NS | EPM3512AQC208-10N |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Aktif | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 512 | — |
| Usable Gates | 10,000 | Up to 10,000 |
| Logic Array Blocks (LABs) | 12 | 16 |
| User I/Os | 172 | 172 |
| Pin-to-Pin Delay (tPD) | 10 ns (speed grade -10) | — |
| Internal Counter Frequency | 227.3 MHz max | — |
| Propagation Delay | 7.5 ns (datasheet figure) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Logic Family | CMOS, EEPROM-based | — |
| Configuration | Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532) | — |
| Kemasan | 208-pin PQFP | 208-pin PQFP (Plastic Quad Flat Pack) |
| Suhu Operasi | 0C to +70C (commercial) | 0 C to 70 C (commercial) |
| ISP Standard | IEEE Std. 1532 | — |
| Status RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status not in verified web data] |
| Jenis Pemasangan | Surface Mount | — |
| Macrocells | — | 512 |
| Tegangan Pemberi Arus | — | 3.3 V |
| Pin-to-Pin Delay | — | 4.5 ns (-10 speed grade) |
| Maximum Internal Frequency | — | 227.3 MHz |
| Speed Grade | — | -10 |
| Process Technology | — | CMOS EEPROM |
| In-System Programming | — | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Built-in, IEEE 1149.1 compliant |
| I/O Standards | — | MultiVolt (1.8V / 2.5V / 3.3V) |