EPM3512AQC208-7N vs EPM3512AQC208-10N Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3512AQC208-7N disebabkan oleh Altera dan EPM3512AQC208-10N disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EPM3512AQC208-7N EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera

EPM3512AQC208-7N ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EPM3512AQC208-7N EPM3512AQC208-10N
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Masa Terakhir Dibeli Obsolete
Family MAX 3000A MAX 3000A
Logic Capacity 512 macrocells, 10,000 usable gates —
Logic Array Blocks (LABs) 32 16
Macrocells per LAB 16 —
User I/Os 172 172
Propagation Delay (tPD) 7.5 ns —
Maximum Frequency (fCNT) 116.3 MHz —
Supply Voltage (VCCINT) 3.3 V (3.0 V to 3.6 V) —
I/O Bank Count 4 (MultiVolt) —
Supported I/O Standards 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS —
Process Technology 0.30 µm CMOS EEPROM CMOS EEPROM
Configuration Non-volatile EEPROM, in-system programmable (ISP) —
JTAG Interface IEEE 1149.1 BST + IEEE 1532 ISP —
Kemasan 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) 208-pin PQFP (Plastic Quad Flat Pack)
Suhu Operasi 0 °C to +70 °C (commercial) 0 C to 70 C (commercial)
Status RoHS Compliant [DATA_NEEDED: RoHS status not in verified web data]
Speed Grade -7 -10
Device Type — CPLD (Complex Programmable Logic Device)
Macrocells — 512
Usable Gates — Up to 10,000
Tegangan Pemberi Arus — 3.3 V
Pin-to-Pin Delay — 4.5 ns (-10 speed grade)
Maximum Internal Frequency — 227.3 MHz
In-System Programming — IEEE Std. 1149.1 JTAG, IEEE Std. 1532
Boundary-Scan Test (BST) — Built-in, IEEE 1149.1 compliant
I/O Standards — MultiVolt (1.8V / 2.5V / 3.3V)

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