EPM5032LC-25 vs EPM5032LC-15 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5032LC-25 disebabkan oleh Altera dan EPM5032LC-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM5032LC-25 | EPM5032LC-15 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | Obsolete |
| Device Family | MAX 5000 | — |
| Architecture | PAL-type EPLD (Erasable Programmable Logic Device) | PAL-type AND/OR with PIA |
| Technology | CMOS, UV-erasable / OTP | CMOS EPROM, 1.0 um process |
| Macrocells | 32 | 32 |
| Product Terms | 320 | — |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 16 bidirectional | — |
| Total Inputs | 24 (7 dedicated + 16 I/O used as input) | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Internal Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V ±10% (4.5 V to 5.5 V) | 5 V (4.75 V to 5.25 V) |
| I/O Standard | 5 V CMOS | — |
| Suhu Operasi | 0 °C to +70 °C (commercial, "LC" suffix) | 0C to +70C (commercial) |
| Kemasan | 28-pin PLCC (JEDEC S-PQCC-J28), 1.27 mm pitch | JLCC-28 (windowed ceramic) |
| Jenis Pemasangan | Surface Mount, socket-compatible | — |
| Configuration Cell | Programmable interconnect array (PIA), OTP / UV-erasable | — |
| Status RoHS | Not RoHS compliant (legacy Altera product) | Non-compliant (contains Pb, ceramic-windowed package) |
| Family | — | MAX 5000 EPLD |
| Usable Gates | — | 600 |
| Logic Array Blocks (LABs) | — | 4 |
| Bidirectional I/O Pins | — | 16 |
| Maximum Operating Frequency | — | 83.3 MHz |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Programmability | — | UV-Erasable / OTP |