EPM5064LC-2 vs EPM5064JC Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5064LC-2 disebabkan oleh Altera dan EPM5064JC disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM5064LC-2 EPM5064JC
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Device Family MAX 5000 —
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 64 64
Logic Array Blocks (LABs) 4 —
Logic Elements per LAB 16 —
Number of Inputs 36 (7 dedicated + 28 I/O) —
Number of I/O Pins 28 —
Number of Flip-Flops 28 —
Propagation Delay (tPD) 45 ns —
Maximum Internal Frequency 40 MHz —
Process Technology CMOS, OTP EPROM (UV-erasable base) —
Programmable Polarity Yes —
Programmable Output Enable Yes, per macrocell —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (typical, 4.75 V - 5.25 V range)
Suhu Operasi -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source] [DATA_NEEDED: operating temperature grade]
Kemasan PLCC-44 (J-Lead, plastic) 68-pin PLCC (JEDEC)
Jenis Pemasangan Surface Mount Surface Mount (socketed)
Status RoHS [DATA_NEEDED: not specified in source] [DATA_NEEDED: RoHS compliance]
Programming Method Altera byte-wide / JTAG programmer —
Family — MAX 5000
Device Type — EPLD (Erasable PLD)
Usable Gates — 1,250 (approx.)
Logic Array Inputs — 36
Logic Array Outputs — 64
I/O Logic Level — TTL / CMOS compatible
Configuration Memory — EPROM (UV-erasable window or OTP)
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: specific tPD grade value]
Maximum Frequency (fMAX) — [DATA_NEEDED: fCNT grade value]
Lead-Free — [DATA_NEEDED: lead-free status]
Aras MSL — [DATA_NEEDED: MSL rating]
Programming Tool — Altera MAX+PLUS II / Quartus II (legacy device support)

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