EPM5192AGC vs EPM5192GC1 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5192AGC disebabkan oleh Altera dan EPM5192GC1 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM5192AGC EPM5192GC1
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 5000 (High-Speed, High-Density MAX 5000 Devices) MAX 5000
Device Type UV-Erasable / OTP Complex PLD (EPLD) CPLD (Complex Programmable Logic Device)
Macrocells 192 —
Logic Density High-density (per MAX 5000 family definition) —
Architecture CMOS, sum-of-products with macrocell output logic —
Process Technology CMOS EPROM-based CMOS
Kemasan 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) —
Speed Grade Suffix C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) —
Suhu Operasi [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
Programmability UV-erasable (windowed package) / One-Time-Programmable (windowless variant) —
Security Bit Programmable security bit (per MAX 5000 family) —
Tegangan Pemberi Arus [DATA_NEEDED: VCC nominal and tolerance] —
Jenis Pemasangan Through-hole (Pin Grid Array) Through-hole (PGA)
Status RoHS Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) unknown
Lifecycle Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) —
Programming Support MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers —
Macro Cells — 192
Usable Gates — 3,750
Maximum Operating Frequency — 62.5 MHz
Supply Voltage (VCC) — 5 V
Programming Technology — UV-Erasable / OTP EPROM
Package Type — Ceramic PGA (Pin Grid Array)
Logic Elements — 192 macrocells with AND/OR array
Propagation Delay — [DATA_NEEDED: tpd specification]
Bilangan Pin — [DATA_NEEDED: pin count for GC1 PGA package]
Development Tool — Altera MAX+PLUS II

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