EPM5192LC vs EPM5192-1LC Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5192LC disebabkan oleh Altera dan EPM5192-1LC disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM5192LC | EPM5192-1LC |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 7000S | MAX 5000 |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 4 |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | — |
| Global Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 55 ns (typical, commercial) | — |
| Maximum Clock Frequency (fMAX) | 50 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | — |
| Process Technology | CMOS, UV-erasable/OTP EPROM configuration | UV EPROM, erasable windowless |
| Programmable Interconnect | Programmable Interconnect Array (PIA), fixed delay | PIA (Programmable Interconnect Array) |
| Boundary-Scan Support | JTAG IEEE 1149.1 | — |
| Programming Interface | JTAG (ByteBlaster-compatible) | — |
| Operating Temperature (commercial) | 0C to +70C | — |
| Kemasan | JLCC-68 (windowed ceramic, LC suffix) | 64-pin Ceramic J-Lead Chip Carrier (LC) |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Status RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic windowless package, lead-bearing termination) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 3,750 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Propagation Delay (tpd) | — | [DATA_NEEDED: -1 speed grade tpd in ns] |
| Tegangan Pemberi Arus | — | 5 V |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| Suhu Operasi | — | 0C to +70C (commercial) |