EPM5192LC1 vs EPM5192LC Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5192LC1 disebabkan oleh Altera dan EPM5192LC disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM5192LC1 | EPM5192LC |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 7000S |
| Device Type | Complex PLD (CPLD), UV-erasable/OTP | — |
| Macrocells | 192 | 192 |
| Equivalent Gates | 3750 | — |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | 64 |
| Kemasan | PQCC-84 (JEDEC S-PQCC-J84, 84-lead Plastic Leaded Chip Carrier) | JLCC-68 (windowed ceramic, LC suffix) |
| Nominal Supply Voltage (VCC) | 5 V | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| Frekuensi Klock Maksimum | 50 MHz | — |
| Propagation Delay (tPD) | 40 ns | 55 ns (typical, commercial) |
| Process Technology | CMOS EPROM | CMOS, UV-erasable/OTP EPROM configuration |
| Programming Method | OTP (LC plastic package); UV-erasable equivalents in JC ceramic package | — |
| Operating Temperature (Commercial 'LC') | 0 °C to 70 °C | — |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| JEDEC Package Code | S-PQCC-J84 | — |
| Logic Array Blocks (LABs) | — | 12 |
| Global Clock Inputs | — | 1 |
| Maximum Clock Frequency (fMAX) | — | 50 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (nominal 5 V) |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA), fixed delay |
| Boundary-Scan Support | — | JTAG IEEE 1149.1 |
| Programming Interface | — | JTAG (ByteBlaster-compatible) |
| Operating Temperature (commercial) | — | 0C to +70C |