EPM7096QC100-7 vs EPM7096QC100-10 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM7096QC100-7 disebabkan oleh Altera dan EPM7096QC100-10 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EPM7096QC100-7 EPM7096QC100-7 - MAX 7000 CPLD, 96 Macrocells, 7.5ns | Altera

EPM7096QC100-7 - MAX 7000 CPLD, 96 Macrocells, 7.5ns | Altera

EPM7096QC100-7 ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EPM7096QC100-7 EPM7096QC100-10
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Masa Terakhir Dibeli Obsolete
Family MAX 7000 MAX 7000
Series MAX 7000 —
Product Type CPLD (Complex Programmable Logic Device) —
Programmable Type EE PLD (EEPROM-based, in-system programmable) —
Macrocells 96 96
User I/Os 76 —
Logic Elements / Gates 1800 gates (typical) —
Pin-to-Pin Delay (tPD) 7.5 ns —
Maximum Frequency (fMAX) 125 MHz —
Supply Voltage - Internal 4.75 V to 5.25 V —
Kemasan / Case 100-BQFP (PQFP-100, 20x14 mm, 0.65 mm pitch) —
Supplier Device Package 100-PQFP (20x14) —
Suhu Operasi 0C to +70C (commercial) 0 °C to +70 °C (commercial)
Program Memory EEPROM (non-volatile, in-system programmable) —
Programming Interface JTAG (IEEE 1149.1) / ByteBlaster ByteBlaster / parallel (JTAG ISP on MAX 7000S variants)
Jenis Pemasangan Surface Mount Surface Mount
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Logic Array Blocks — 4
User I/O Pins — 76
Propagation Delay (tPD) — 10 ns
Maximum Operating Frequency — 100 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V
Technology — EEPROM-based CMOS
Boundary Scan — IEEE Std. 1149.1 (JTAG) on MAX 7000S
PCI Compliance — Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade)
Kemasan — 100-pin PQFP (R-PQFP-G100, 20×14 mm, 0.65 mm pitch)

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