EPM7256AETC144-10N vs EPM3256ATC144-10N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM7256AETC144-10N disebabkan oleh Intel dan EPM3256ATC144-10N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Intel
EPM7256AETC144-10N - MAX 7000A 256-Macro CPLD, 10ns TQFP-144 | Intel
EPM7256AETC144-10N ObsoleteAltera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EPM7256AETC144-10N | EPM3256ATC144-10N |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Masa Terakhir Dibeli |
| Family | MAX 7000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 5,000 | 5,000 (up to 10,000 usable in family) |
| Macro Cells | 256 | 256 |
| Logic Array Blocks | 16 | — |
| Maximum User I/O Pins | 120 (in 144-pin TQFP) | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency | 95.2 MHz | — |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Voltage Tolerance | 5 V-tolerant | — |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | — |
| Programming Interface | IEEE 1149.1 JTAG (ISP) | — |
| Kemasan | TQFP-144 (ETC suffix) | 144-LQFP (TQFP, ATC suffix) |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Suhu Operasi | -40C to +85C (industrial) | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] |
| Technology | CMOS, EEPROM-based | — |
| Pin Compatibility | Pin-compatible with 5.0V MAX 7000S family | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] |
| Series | — | MAX 3000A |
| Number of I/Os | — | 116 |
| Number of Logic Elements / Blocks | — | 16 LABs |
| Supply Voltage (VCCINT) | — | 3.3 V |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| Global Clocks | — | 3 |
| Global Clear / OE | — | Yes (1 global clear, 1 global OE) |
| Program Memory Type | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Support | — | IEEE Std. 1149.1 with pin-locking |
| ISP Compliance | — | IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Built-in, IEEE 1149.1 compliant |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: not explicitly confirmed in verified data] |