EPM9320LC84-15 vs EPM9320LC84-20N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9320LC84-15 disebabkan oleh Intel dan EPM9320LC84-20N disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM9320LC84-15 | EPM9320LC84-20N |
|---|---|---|
| Merek | Intel | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Aktif |
| Family | MAX 9000 | — |
| Series | EPM9320 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 | 6,000 |
| Logic Array Blocks (LABs) | 20 | — |
| Propagation Delay (tPD) | 15 ns (max) | 16 ns |
| Frekuensi Klock Maksimum | 117.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) | 5 V |
| Programmability | 5.0 V in-system programmable (ISP) via JTAG | — |
| JTAG Interface | IEEE Std. 1149.1 boundary-scan compliant | — |
| Kemasan | 84-pin PLCC (Plastic Leaded Chip Carrier) | — |
| Jenis Pemasangan | Surface Mount | Surface Mount (J-bend) |
| Suhu Operasi | -40C to +85C (commercial) [DATA_NEEDED: exact grade] | 0 C to +70 C (Commercial) |
| Technology | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) | — |
| Built-in Pull-up Resistors | Yes, on every I/O pin | — |
| Architecture Feature | Pin-locking across design iterations | — |
| Status RoHS | [DATA_NEEDED: confirm from manufacturer] | [DATA_NEEDED: RoHS compliance status] |
| Logic Family | — | CMOS (EEPROM-based) |
| User I/Os | — | 60 |
| Bilangan Pin | — | 84 |
| Package Type | — | Plastic Leaded Chip Carrier (PLCC-84, J-bend) |
| Package Code | — | QCCJ |
| Internal Frequency | — | 118 MHz |
| Programming | — | 5.0-V In-System Programmable via JTAG (IEEE 1149.1) |
| Terminal Form | — | J BEND |
| Aras MSL | — | [DATA_NEEDED: MSL moisture sensitivity level] |