EPM9560RC208-20N vs EPM9560RC210-20 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9560RC208-20N disebabkan oleh Intel dan EPM9560RC210-20 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera
EPM9560RC210-20 ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EPM9560RC208-20N | EPM9560RC210-20 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Masa Terakhir Dibeli |
| Device Family | MAX 9000 (EPM9560) | — |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 12,000 |
| Propagation Delay (tPD) | 20 ns | — |
| Kemasan | 208-pin RQFP (PowerQuad Flat Pack) | RQFP-210 (Power Quad Flat Pack, 0.5mm pitch) |
| User I/O Pins | 149 | — |
| Tegangan Pemberi Arus | 5.0 V | 5 V |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (MAX+PLUS II flow) |
| JTAG Interface | IEEE Std. 1149.1 | — |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Suhu Operasi | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: commercial 0C to 70C typical; industrial variants exist] |
| Status RoHS | Lead-free (N suffix) | RoHS3 Compliant (per supplier listing) |
| Logic Architecture | Multiple Array MatriX (MAX), third-generation CMOS EEPROM | — |
| Flip-Flops | 772 (per EPM9560 series data) | — |
| Speed Grade | -20 (20 ns) | — |
| Aras MSL | [DATA_NEEDED: MSL level] | — |
| Family | — | MAX 9000 |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 16 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Clock-to-Output (tCO) | — | 12 ns |
| Maximum User I/O | — | [DATA_NEEDED: 212 I/O per datasheet, package-dependent] |
| Process Technology | — | 0.65 um EEPROM |
| Boundary-Scan (JTAG) | — | IEEE Std 1149.1 compliant |