EPM9560RI304-20N vs EPM9560RI304-15 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9560RI304-20N disebabkan oleh Intel dan EPM9560RI304-15 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM9560RI304-20N | EPM9560RI304-15 |
|---|---|---|
| Merek | Intel | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | — |
| Logic Array Blocks (LABs) | 35 | — |
| Maximum User I/O Pins | 212 | — |
| Pin-to-Pin Propagation Delay (tPD) | 20 ns | — |
| Internal Performance Grade | 100 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | 4.5 V to 5.5 V (5 V typical) |
| Process Technology | CMOS EEPROM-based | 0.5 µm CMOS EEPROM |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | — |
| Kemasan | 304-pin RQFP (Plastic Quad Flat Pack) | — |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Suhu Operasi | -40C to +85C (industrial; verify per lot) | 0 C to 70 C (commercial) |
| Status RoHS | Unknown (legacy Altera part - confirm per lot) | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 9000 |
| Architecture | — | Multiple Array MatriX (MAX) - EEPROM-based CPLD |
| Flip-Flops | — | 772 |
| User I/Os | — | 212 (216 per some datasheets) |
| Dedicated Inputs | — | 4 |
| Total Terminals | — | 304 |
| Package Code | — | HFQFP / S-PQFP-G304 |
| Package Type | — | 304-pin RQFP (Quad Flat Pack, gull-wing) |
| Propagation Delay (tpd) | — | 11.4 ns (per digchip datasheet); 16.6 ns reported by MicrochipUSA |
| Maximum Internal Frequency | — | 145 MHz |
| Speed Grade | — | -15 |
| I/O Logic Levels | — | 3.3 V or 5 V configurable |
| Temperature Grade | — | Industrial (per Partstack listings) |
| Logic Family | — | CMOS |
| Programming | — | 5.0-V in-system programmable via JTAG (IEEE 1149.1) |