RTAX250SL-LG624E vs RTAX250SL-1CG624E Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci RTAX250SL-LG624E disebabkan oleh Microsemi dan RTAX250SL-1CG624E disebabkan oleh Microchip Technology. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Microchip Technology
RTAX250SL-1CG624E - 250K Gate Rad-Tolerant FPGA, CCGA-624 | Microchip
RTAX250SL-1CG624E ✓ AktifPengandingan Spesifikasi
| Parametr | RTAX250SL-LG624E | RTAX250SL-1CG624E |
|---|---|---|
| Merek | Microsemi | Microchip Technology |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Aktif | Aktif |
| Manufacturer | Actel (Microsemi / Microchip Technology) | — |
| Family | RTAX-SL Radiation-Tolerant FPGA | — |
| Equivalent System Gates | 250000 gates | 250,000 gates |
| Logic Cells (CLBs) | 2816 cells | — |
| Maximum System Frequency | 649 MHz | 649 MHz |
| Process Technology | 0.15 um CMOS | 0.15 um CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V (1.425 V to 1.575 V) |
| Kemasan | 624-Pin LGA (LG624) | 624-ball Ceramic Column Grid Array (CCGA-624) |
| Jenis Pemasangan | Surface Mount | Surface Mount (ceramic column grid array) |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| Radiation Tolerance | Radiation-tolerant, space-flight qualified family | SEU-immune to specified LET threshold; SEU rate < 10-10 errors/bit-day |
| Live at Power-Up | Yes | — |
| Clock Architecture | Segmentable clocks, chip-wide highway routing | — |
| Arithmetic Support | Dedicated carry logic | — |
| Speed Grade | Standard (-) per RTAX-S/SL speed grade system | — |
| Suhu Operasi | [DATA_NEEDED: operating temperature range] | -55C to +125C |
| I/O Count (LG624) | [DATA_NEEDED: user I/O count for LG624 package] | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Configurable Logic Blocks (CLBs) | — | 2816 |
| Logic Cells | — | 4224 |
| User I/O | — | 248 inputs / 248 outputs |
| Maximum Combinatorial Delay (CLB) | — | 0.93 ns |
| Logic Family | — | CMOS |
| SEU Mitigation | — | SEU-hardened registers (no external TMR required) |
| Configuration | — | Live-at-power-up, true single-chip operation |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O bank voltage] |