5PB1106CMGI - 1:6 LVCMOS Clock Buffer 200MHz QFN-16 | Renesas
MPN: 5PB1106CMGI ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2.02 | $2.02 |
| 10 | $1.85 | $18.50 |
| 100 | $1.62 | $162.00 |
| 500 | $1.41 | $705.00 |
| 1,000 | $1.18 | $1,180.00 |
| 2,500 | $1.02 | $2,550.00 |
5PB1106CMGI Overview
A clock buffer (or fanout buffer) is a timing IC that replicates a single reference clock into multiple identical copies, each driving a separate load while preserving phase, frequency, and edge-rate fidelity. Within the broader clock-tree hierarchy, clock buffers sit between PLLs, oscillators, or upstream generators and downstream loads such as SoCs, FPGAs, memory controllers, and high-speed transceivers. They are essential when a source cannot drive all loads directly due to fanout limits or routing asymmetry.
The 5PB1106CMGI delivers 50 fs RMS additive phase jitter (12 kHz to 20 MHz integration), a low propagation delay of ~3 ns typical, and output-to-output skew under 100 ps. It supports LVCMOS input levels on the primary input pin and reproduces them on six outputs, all sourced from a common internal tree. The Output Enable pin allows system-level power sequencing, while internal termination minimizes external component count.
Architecturally, the device combines a low-jitter input receiver, a precision matched-delay distribution tree, and six LVCMOS output drivers with controlled slew rate. This design ensures that adding the buffer contributes minimal jitter to upstream PLLs, preserving signal integrity in jitter-sensitive SERDES, ADC/DAC sampling clocks, and FPGA reference inputs. The wide 1.8 V to 3.3 V supply range enables direct interface with modern low-voltage processors without level translation.
Typical applications include distributing a baseband reference clock to FPGAs and ASICs, driving multiple DDR memory channels, networking switch/router clock trees, PCIe reference clock fanout, and test/measurement instrumentation. In PCIe Gen 3/4 systems, the part meets the additive jitter budget needed for 100 MHz reference distribution.
When designing with the 5PB1106CMGI, route the six outputs with matched trace lengths to preserve the on-chip skew budget, place the supply decoupling within 2 mm of the VDD pins, and leave the exposed pad soldered to a continuous ground plane for thermal relief.
This page synthesizes distributor pricing, drop-in alternative coverage, and practical design notes that go beyond the manufacturer datasheet to support faster design-in decisions for the 5PB1106 family.
Drop-in alternatives for 5PB1106CMGI — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with 5PB1106CMGI (same form factor and footprint) — differing in Number of Outputs.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
5PB1106CMGI8
✅ Drop-In✓ In Stock
$1.18 / Unit
View Datasheet →5PB1106PGGI
✅ Drop-In📋 Reference alternative (not in catalog)
5PB1106CMGI/N
✅ Drop-In📋 Reference alternative (not in catalog)
5PB1106CMGI Specifications
| Function | Clock Fanout Buffer (Distribution) |
| Number of Inputs | 1 |
| Number of Outputs | 6 |
| Ratio - Input:Output | 1:6 |
| Output Logic Type | LVCMOS |
| Input Logic Type | LVCMOS |
| Maximum Output Frequency | 200 MHz |
| Supply Voltage Range | 1.8 V to 3.3 V |
| Additive Phase Jitter (RMS) | 50 fs (12 kHz to 20 MHz) |
| Output Enable | Yes |
| Operating Temperature Range | -40 C to +85 C (industrial) |
| Package | 16-pin QFN (UFQFN), 3x3 mm |
| Mounting Type | Surface Mount |
| MSL Level | 1 (unlimited floor life at <30 C / 85% RH) |
| RoHS Status | Compliant |
| Lead-Free / Halogen-Free | Yes |
| Supplier Package Designator | CMGI (Renesas 16-QFN) |
5PB1106CMGI Pin Configuration
| Pin 1 | OE — Output Enable (active-high; pull low to tri-state outputs) |
| Pin 2 | IN — LVCMOS clock input |
| Pin 3 | VDD — Supply voltage (1.8 V to 3.3 V) |
| Pin 4 | GND — Ground |
| Pin 5 | Q0 — LVCMOS clock output 0 |
| Pin 6 | Q1 — LVCMOS clock output 1 |
| Pin 7 | Q2 — LVCMOS clock output 2 |
| Pin 8 | Q3 — LVCMOS clock output 3 |
| Pin 9 | Q4 — LVCMOS clock output 4 |
| Pin 10 | Q5 — LVCMOS clock output 5 |
| Pin 11 | VDD — Supply voltage (1.8 V to 3.3 V) |
| Pin 12 | GND — Ground |
| Pin 13 | NC — Not connected (per datasheet) |
| Pin 14 | NC — Not connected (per datasheet) |
| Pin 15 | NC — Not connected (per datasheet) |
| Pin 16 | EP — Exposed pad - thermal/ground, must be soldered to PCB GND plane |
Typical Applications
5PB1106CMGI is suitable for 6 applications: PCIe Reference Clock Distribution, Networking Switch / Router Clock Tree, FPGA / ASIC Reference Clock Fanout, DDR Memory Controller Clock Distribution, Test & Measurement Instrumentation, Industrial Automation & Motor Control.
PCIe Reference Clock Distribution
The 5PB1106CMGI distributes a 100 MHz PCIe reference clock from a single source to up to six downstream loads. Its 50 fs RMS additive phase jitter (12 kHz to 20 MHz) sits well inside the PCIe Gen 3/4 jitter budget, so the buffer does not degrade upstream PLL phase noise. Six matched outputs let one buffer feed root complex, switch, endpoint, and BMC clock pins on a server or add-in card. The 1.8 V to 3.3 V supply matches modern serializer reference inputs without level translation. Place the part close to the reference clock source, keep output traces length-matched within 5 mm, and tie the exposed pad to a continuous ground pour for thermal relief.
Recommended
Networking Switch / Router Clock Tree
Ethernet switches and routers require clean 156.25 MHz or 161.13 MHz reference clocks to be fanned out to multiple PHYs, MACs, and SERDES channels. The 5PB1106CMGI's 200 MHz output capability easily covers these common telecom frequencies, and its 50 fs RMS additive jitter preserves the eye diagram of 10G/25G links. Six outputs are sufficient to drive several switch ports plus the management controller from one reference oscillator. The Output Enable pin supports per-port power gating for energy-efficient Ethernet (EEE) designs. Use star routing from the buffer outputs to each PHY, with 50 ohm controlled impedance traces.
Recommended
FPGA / ASIC Reference Clock Fanout
Modern FPGAs and ASICs often require the same reference clock on multiple clock input pins (e.g., transceiver reference banks and fabric global clock inputs). The 5PB1106CMGI's six matched outputs, <100 ps output-to-output skew, and low additive jitter make it ideal for fanning out a single oscillator to all required pins. The 16-QFN 3x3 mm footprint fits easily underneath or beside the FPGA on the same board layer. Its LVCMOS input is compatible with standard FPGA clock output standards such as LVCMOS18/25/33. Decouple VDD with a 100 nF ceramic within 2 mm of the supply pin and add a 10 uF bulk capacitor nearby.
Recommended
DDR Memory Controller Clock Distribution
DDR3/DDR4 memory subsystems often require the DDR controller clock (typically 200-400 MHz) to be fanned out to multiple DIMM slots, memory down devices, and the controller itself. The 5PB1106CMGI delivers up to 200 MHz, which covers DDR3 clock frequencies and the lower end of DDR4 base clocks. Its matched outputs and tight skew budget maintain timing alignment between DIMMs, preventing setup/hold violations across ranks. The 1.8 V to 3.3 V supply range supports 1.5 V DDR3 or 1.2 V DDR4 designs when paired with appropriate level shifting. Use length-matched fly-by topology from the buffer outputs to each DIMM clock pin.
Recommended
Test & Measurement Instrumentation
Test equipment, oscilloscopes, and signal analyzers require ultra-low-jitter reference clocks for accurate ADC sampling. The 5PB1106CMGI's 50 fs RMS additive jitter does not degrade the noise floor of high-resolution measurement, and its six outputs let one buffer drive a front-end ADC, a trigger circuit, a back-end DAC, and a synchronization port simultaneously. The 1.8 V to 3.3 V supply covers typical ADC auxiliary rails. Compact 16-QFN packaging suits dense multi-channel instruments. Pair the buffer with a low-noise OCXO or MEMS oscillator as the upstream source for best results.
Recommended
Industrial Automation & Motor Control
Industrial servo controllers and PLCs need deterministic reference clocks for EtherCAT, PROFINET, or SERCOS fieldbuses. The 5PB1106CMGI distributes a master reference (e.g., 50 MHz or 100 MHz) to motor control ASICs, encoder interfaces, and communication PHYs with six matched outputs. The -40 C to +85 C industrial temperature range supports factory floor deployment. The Output Enable pin enables safe clock shutdown during emergency stop events. The 1.8 V to 3.3 V supply lets the buffer share power rails with modern motor controller SoCs. Use shielded routing if the buffer sits near power electronics.
Recommended
Recommended Products Summary
Engineering reference data for 5PB1106CMGI — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5PB1106CMGI8 | 5PB1106CMGI/N |
|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 16-pin QFN (UFQFN) 3x3 mm | 16-pin QFN (UFQFN) 3x3 mm - same | 16-pin QFN (UFQFN) 3x3 mm - same |
| Function | 1:6 LVCMOS Clock Buffer | 1:6 LVCMOS Clock Buffer | 1:6 LVCMOS Clock Buffer |
| Maximum Output Frequency | 200 MHz | 200 MHz | 200 MHz |
| Additive Phase Jitter (RMS) | 50 fs | 50 fs | 50 fs |
| Supply Voltage Range | 1.8 V to 3.3 V | 1.8 V to 3.3 V | 1.8 V to 3.3 V |
| Output Enable | Yes | Yes | Yes |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| RoHS Compliance | Yes | Yes | Yes |
Key Differentiators
- Best-in-class 50 fs RMS additive jitter for clean reference clock distribution (vs Generic 1:6 LVCMOS clock buffers)
- Wide 1.8 V to 3.3 V supply range eliminates level shifters (vs Fixed 3.3 V-only clock buffers)
- Compact 16-QFN 3x3 mm footprint for dense clock trees (vs Larger TSSOP-14 footprint 5PB1106PGGI variant)
Design Notes
Place the 5PB1106CMGI within 25 mm of the upstream reference oscillator or PLL output. Decouple VDD with a 100 nF X7R ceramic capacitor within 2 mm of each VDD pin, and add a single 10 uF bulk capacitor on the same supply rail. The exposed pad must be soldered to a continuous ground plane that covers at least 1 square inch of top-layer copper. Route all six outputs with matched trace lengths (within 5 mm target, 12.5 mm max) using 50 ohm controlled impedance to preserve output-to-output skew. Keep input and output traces on the same layer or use tightly coupled stripline to avoid impedance discontinuities.
The 5PB1106CMGI contributes 50 fs RMS additive jitter, which is negligible compared to typical 100 MHz oscillator phase noise of ~150 fs RMS. Do NOT route the input clock through long traces or noisy switching planes because that external jitter will dominate. Place a 33 ohm series damping resistor at the input if the upstream source has fast edges (<500 ps) or the trace length exceeds 25 mm. Avoid routing the buffer outputs over split ground planes or across switching power supply islands.
Do not float the Output Enable (OE) pin; tie it directly to VDD if unused, or to a GPIO with a 10 kohm pull-up. Floating OE can leave outputs in an indeterminate state at power-up. Do not exceed the 200 MHz maximum output frequency; over-clocking causes degraded jitter and rise/fall time. Do not load any output beyond the rated drive strength, and avoid mixing AC-coupled and DC-coupled loads on different outputs because the buffer is designed for DC-coupled LVCMOS only. Finally, do not skip the exposed-pad solder connection because it is the primary thermal path.
Compliance Information
RoHS and lead-free confirmed by Renesas product page and DigiKey/Mouser listings. Not AEC-Q100 qualified; the part targets commercial and industrial (-40 C to +85 C) segments rather than automotive.
