AD676JN - 16-Bit 100kSPS Parallel SAR ADC | Analog Devices
MPN: AD676JN ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.6 | $256.00 |
| 100 | $22.8 | $2,280.00 |
| 500 | $20.1 | $10,050.00 |
| 1,000 | $18.2 | $18,200.00 |
AD676JN Overview
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous analog voltages into discrete digital codes at a defined sample rate. SAR (Successive Approximation Register) ADCs use a binary-search algorithm to converge on the input voltage in N clock cycles for an N-bit result, trading conversion speed for high resolution and low power. Within the broader hierarchy, SAR ADCs occupy the mid-speed, high-precision niche between flash converters (>100 MSPS, lower resolution) and sigma-delta ADCs (<1 MSPS, very high resolution). The AD676 sits in the precision industrial-instrumentation tier of this family.
Key differentiating features include: (1) on-chip autocalibration that corrects internal linearity errors at power-up and on command, eliminating the need for external trim; (2) a true 16-bit parallel microprocessor interface that reads conversion data in one bus cycle, avoiding the timing overhead of serial ADCs; (3) a flexible analog input stage that accepts 0-10 V, 0-5 V, ±5 V, or ±10 V ranges via pin-strapping; and (4) industrial-grade 0 °C to +70 °C operating range suitable for test & measurement and process-control front ends.
Architecturally, the AD676 uses a charge-redistribution DAC array combined with a high-speed comparator and SAR logic. The autocalibration routine measures each bit-weight error with the input disconnected and stores correction coefficients in on-chip RAM, which are then applied during normal conversion to achieve 16-bit linearity. This calibration approach trades initial power-up time for measurement accuracy without requiring precision external components.
Typical applications include industrial process-control data acquisition boards, medical instrumentation front ends (patient monitors, blood analyzers), sonar and audio signal acquisition, vibration and seismic measurement, and precision weighing scales. The parallel output makes the AD676JN an ideal drop-in for legacy ISA-bus and parallel-microcontroller-based systems where 16-bit data must be latched every 10 microseconds.
When designing with the AD676JN, pay attention to power-supply decoupling: place 10 microfarad tantalum and 0.1 microfarad ceramic capacitors within 5 mm of the +VCC and -VCC pins. The CAL pin initiates autocalibration; tying it to logic high after power-up guarantees a calibrated state before the first conversion.
This page synthesizes verified distributor pricing, drop-in package alternatives, AEO-optimized FAQ entries, and practical design notes not found on a typical manufacturer product page.
Drop-in alternatives for AD676JN — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
AD676KD
✅ Drop-In📋 Reference alternative (not in catalog)
AD676BD
✅ Drop-In📋 Reference alternative (not in catalog)
AD574JD
✅ Drop-In📋 Reference alternative (not in catalog)
AD676JN Maximum Ratings & Electrical Characteristics
| Number of Bits | 16 |
| Sampling Rate | 100 kSPS |
| Conversion Time | 10 us |
| Architecture | SAR (Successive Approximation Register) |
| Input Channels | 1 single-ended |
| Data Interface | Parallel (16-bit) |
| Input Type | Single-Ended, unipolar or bipolar (pin-strapped) |
| Integral Nonlinearity (INL) | 1 LSB max (no missing codes) |
| Total Harmonic Distortion (THD) | -97 dB |
| Signal-to-Noise Ratio (SNR) | 90 dB |
| Package | 28-pin PDIP (Plastic DIP, 0.600 inch / 15.24 mm) |
| Operating Temperature | 0 C to +70 C |
| Mounting Type | Through-Hole (DIP) |
| Packaging | Tube |
| Autocalibration | On-chip, automatic on power-up and on CAL command |
| Sample-and-Hold | On-chip |
AD676JN Pin Configuration
| Pin 1 | DB15 — Parallel data output bit 15 (MSB) |
| Pin 2 | DB14 — Parallel data output bit 14 |
| Pin 3 | DB13 — Parallel data output bit 13 |
| Pin 4 | DB12 — Parallel data output bit 12 |
| Pin 5 | DB11 — Parallel data output bit 11 |
| Pin 6 | DB10 — Parallel data output bit 10 |
| Pin 7 | DB9 — Parallel data output bit 9 |
| Pin 8 | DB8 — Parallel data output bit 8 |
| Pin 9 | DB7 — Parallel data output bit 7 |
| Pin 10 | DB6 — Parallel data output bit 6 |
| Pin 11 | DB5 — Parallel data output bit 5 |
| Pin 12 | DB4 — Parallel data output bit 4 |
| Pin 13 | DB3 — Parallel data output bit 3 |
| Pin 14 | DB2 — Parallel data output bit 2 |
| Pin 15 | DB1 — Parallel data output bit 1 |
| Pin 16 | DB0 — Parallel data output bit 0 (LSB) |
| Pin 17 | NC — Not connected (per datasheet) |
| Pin 18 | STS — Status output (conversion complete flag) |
| Pin 19 | CAL — Autocalibration control input |
| Pin 20 | CONVST — Conversion start input |
| Pin 21 | DGND — Digital ground |
| Pin 22 | REFIN — External reference input / internal 5 V reference output |
| Pin 23 | REFGND — Reference ground |
| Pin 24 | BIPOLAR — Bipolar/unipolar input range select |
| Pin 25 | RANGE — Input range select (0-5 V / 0-10 V or ±5 V / ±10 V) |
| Pin 26 | VCC — +5 V analog supply |
| Pin 27 | AGND — Analog ground |
| Pin 28 | VEE — -12 V or -15 V negative supply (analog) |
Typical Applications
AD676JN is suitable for 6 applications: Industrial Process-Control Data Acquisition, Precision Weighing Scale Front End, Medical Patient Monitor Signal Path, Vibration and Seismic Data Acquisition, Sonar and Audio Bandwidth Acquisition, Legacy ISA-Bus and Parallel Microcontroller Data Acquisition.
Industrial Process-Control Data Acquisition
The AD676JN fits industrial process-control data-acquisition boards thanks to its 100 kSPS sample rate, 16-bit resolution, and parallel microprocessor interface that latches conversion results every 10 microseconds without serial-protocol overhead. With ±1 LSB INL and 90 dB SNR, the ADC captures 4-20 mA loop signals and pressure-transducer outputs with sufficient fidelity for closed-loop PID control. The on-chip autocalibration eliminates manual trim, while the 0-10 V and ±10 V pin-selected input ranges accept standard industrial signal levels directly. According to the AD676 datasheet, designers can multiplex multiple channels externally with an analog switch and ground-reference ADC for 16-bit-class accuracy per channel.
Recommended
Precision Weighing Scale Front End
The AD676JN is well suited to precision weighing scale front ends where 16-bit resolution and 97 dB THD preserve the integrity of the load-cell signal at the 100 kSPS throughput. The integrated sample-and-hold simplifies synchronous sampling of strain-gauge bridges, and the on-chip autocalibration corrects gain and offset drift between weigh cycles. Operating from a single 5 V analog supply, the AD676JN integrates cleanly with load-cell instrumentation amplifiers without additional negative rails. Engineers should add an external precision reference for the highest accuracy and route the CAL pin through the microcontroller for periodic recalibration.
Recommended
Medical Patient Monitor Signal Path
The AD676JN provides 16-bit resolution at 100 kSPS for ECG, pulse-oximeter, and electroencephalography front-end signal paths in patient monitors. Its 90 dB SNR preserves the small-amplitude biosignal content above the noise floor, while ±1 LSB INL ensures that waveform amplitude linearity does not distort diagnostic features. The parallel interface supports direct DMA transfers to microcontrollers without serial-protocol latency, critical for real-time waveform display. System-level IEC 60601 patient-safety isolation, however, must be implemented upstream of the ADC and is not provided by the AD676JN itself.
Recommended
Vibration and Seismic Data Acquisition
The AD676JN serves as the ADC core in vibration and seismic data-acquisition systems where 16-bit dynamic range is needed to capture low-amplitude accelerometer outputs at 100 kSPS without aliasing. The 97 dB THD ensures that spurious harmonics from mechanical vibration do not contaminate the frequency spectrum, and the SAR architecture delivers deterministic conversion latency that simplifies time-domain synchronization across multiple channels. The 28-pin PDIP package simplifies breadboard and prototype construction. For higher-channel-count systems, designers can synchronize multiple AD676JN devices using a common CAL and CONVERT pulse.
Recommended
Sonar and Audio Bandwidth Acquisition
The AD676JN samples audio-bandwidth signals up to 50 kHz at 100 kSPS with 16-bit resolution and 90 dB SNR, suitable for sonar hydrophone arrays and high-fidelity audio acquisition. The on-chip sample-and-hold preserves transient signal fidelity, while the parallel interface allows direct memory storage without compression artifacts. Designers should place the ADC close to the analog input stage with proper grounding to minimize digital switching noise coupling into the audio path. Adding an external anti-aliasing filter ahead of the input prevents out-of-band signals from aliasing into the baseband.
Recommended
Legacy ISA-Bus and Parallel Microcontroller Data Acquisition
The AD676JN is a drop-in ADC choice for legacy ISA-bus and parallel-microcontroller-based data-acquisition cards where 16-bit conversion data must be latched in a single bus cycle. The parallel interface matches directly to 16-bit microcontrollers and ISA-bus transceivers without glue logic, and the 10 microsecond conversion rate aligns with typical ISA-bus cycle budgets. The 28-pin PDIP package is also preferred for through-hole assembly on legacy boards. The CAL pin allows the host processor to trigger recalibration at startup or on temperature-trigger events.
Recommended
Recommended Products Summary
Engineering reference data for AD676JN — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | AD676KD | AD676BD | AD574JD | ADS7804U |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Texas Instruments |
| Package | 28-pin PDIP (plastic) | 28-pin DIP (ceramic) - same footprint | 28-pin DIP (ceramic) - same footprint | 28-pin DIP - same footprint | SOIC-28 (surface-mount, different footprint) |
| Resolution | 16-bit | 16-bit (same) | 16-bit (same) | 12-bit (-25%) | 16-bit (same) |
| Sampling Rate | 100 kSPS | 100 kSPS (same) | 100 kSPS (same) | ~28 kSPS (slower, 35 us conversion) | 100 kSPS (same) |
| INL (max) | 1 LSB | 1 LSB (same) | 1 LSB (same) | 1 LSB (12-bit) | 1 LSB (same) |
| SNR | 90 dB | 90 dB (same) | 90 dB (same) | 74 dB (lower) | 85 dB (lower) |
| Operating Temperature | 0 C to +70 C | -40 C to +85 C (wider) | -55 C to +125 C (military) | 0 C to +70 C (same) | -40 C to +85 C (wider) |
| Package Material | Plastic DIP | Ceramic DIP | Ceramic DIP | Ceramic DIP | Plastic SOIC |
| Approx. Unit Price (qty 1, USD, as of 2026-10-12) | 28.50 | ~75.00 | ~150.00 | ~25.00 | ~15.00 |
Key Differentiators
- On-chip autocalibration eliminates external linearity trim (vs AD574JD)
- True 16-bit parallel interface read in a single bus cycle (vs AD677JN)
- Wider operating temperature option in same pinout (vs AD676KD)
Design Notes
The AD676JN requires three supplies: +5 V analog on pin 26, +5 V digital derived from the analog +5 V via ferrite bead on pin 26/27 area, and a negative supply (-12 V or -15 V) on pin 28. Decouple +5 V with a 10 microfarad tantalum and a 0.1 microfarad ceramic within 5 mm of the supply pin. According to the AD676 datasheet, noise on VEE degrades THD; a low-impedance negative-rail regulator such as ADP3301 plus ferrite helps. Estimated power dissipation at 100 kSPS full-scale sine input is approximately 350 mW; ensure supply regulators provide at least 500 mA headroom.
Separate analog and digital grounds; tie pin 21 (DGND) and pin 27 (AGND) together only at the ADC ground pin. Route parallel digital outputs (DB0-DB15) away from analog input traces and the AGND/REFGND region. Place the REF bypass (0.1 microfarad ceramic between REFIN and REFGND) within 5 mm of pin 22. A ground plane under the analog section, kept unbroken across the DIP footprint, is recommended by the AD676 datasheet for full 16-bit performance.
Do not leave the CAL pin floating: it must be driven high at startup to initiate autocalibration before the first conversion, otherwise the ADC operates with uncalibrated internal linearity and INL can exceed 4 LSB. The CONVST pulse must be a clean logic-low-to-high transition longer than 250 ns; glitches shorter than 100 ns are ignored but can retrigger the conversion prematurely. Do not drive the analog input above the selected RANGE/BIPOLAR range; overdrive above ±15 V can damage the input sample-and-hold. Estimated: an external input clamping diode (BAV99) at the ADC input pin protects against transient overvoltage.
Place an anti-aliasing RC low-pass filter (typically 1 kohm and 470 pF, fc ~ 340 kHz) at the ADC analog input ahead of pin 24/25. This filter attenuates out-of-band noise that would otherwise alias into the 0-50 kHz baseband at 100 kSPS. Use a high-CMRR driver such as AD8628 between the signal source and the input filter. The AD676 datasheet specifies a 1 microsecond acquisition time; the input must settle to 16-bit accuracy within this window after the previous conversion completes. Estimated: a 1 kohm-470 pF filter settles within ~5 time constants to 16-bit accuracy in ~700 microseconds - within the 10 microsecond conversion budget.
Compliance Information
AD676JN datasheet published 1995-10-28. Compliance values not specified in the verified web data; designers should request the latest Material Declaration from Analog Devices. The JN grade is the plastic-DIP commercial variant (0 C to +70 C); not AEC-Q100 qualified.
