AD7878JPZ-REEL - 12-Bit 100kHz SAR ADC | Analog Devices
MPN: AD7878JPZ-REEL ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $17.5 | $17.50 |
| 10 | $15.8 | $158.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $12.2 | $6,100.00 |
| 1,000 | $10.85 | $10,850.00 |
AD7878JPZ-REEL Overview
A successive-approximation-register ADC is a converter architecture that resolves one bit per clock cycle using an internal binary-weighted capacitor network and a comparator, then a digital-to-analog converter (DAC). This topology delivers deterministic latency, excellent DC accuracy, and inherently anti-alias-friendly sampling, making it preferred for multiplexed data-acquisition systems, motor-control feedback loops, and DSP front-ends where latency must be bounded. Within the broader converter hierarchy, SAR ADCs sit between flash converters (fastest, lowest resolution) and sigma-delta ADCs (highest resolution, lowest bandwidth), with the AD7878 occupying the high-speed 12-bit niche favored in industrial control and instrumentation.
Key features of the AD7878JPZ-REEL include: 8.3 kSamples/sec nominal throughput (per third-party spec sheet), 2 us track/hold acquisition time, 7 us conversion time, internal 3 V Zener reference, 8-word FIFO buffer for DSP handshake efficiency, and on-chip DSP-compatible serial interface logic. The LC2MOS (Linear Compatible CMOS) process combines precision bipolar analog stages with low-power CMOS digital logic, enabling the integrated DSP-ready interface without external glue logic. The commercial temperature grade (0 C to +70 C) suits indoor industrial, instrumentation, and laboratory equipment.
Typical applications span process-control front-ends, multiplexed data-acquisition systems, DSP-input signal chains, motor-control position feedback, and laboratory instrumentation. The on-chip FIFO is particularly valuable when the host processor (DSP or microcontroller) cannot service every conversion interrupt; the 8-word depth absorbs timing jitter and reduces interrupt overhead.
When designing with this part, ensure both +5 V (VDD) and -5 V (or -3 V) negative supplies are decoupled with 0.1 uF ceramic capacitors placed within 5 mm of the supply pins, and observe the maximum throughput vs. acquisition/conversion timing budget described in the datasheet timing section. The bipolar input requires input-signal conditioning to scale within the ±3 V (default) or ±10 V (with attenuation) input range.
This page synthesizes distributor pricing, drop-in same-package alternatives, and PCB-level design guidance not found in the bare manufacturer datasheet, with parameters sourced from Analog Devices, DigiKey, Mouser, Octopart, and third-party spec repositories as of 2026-10-12.
Drop-in alternatives for AD7878JPZ-REEL — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with AD7878JPZ-REEL (same form factor and footprint) — differing in Conversion Time, Operating Temperature, Package, Track/Hold Acquisition Time.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
AD7878JPZ
✅ Drop-In📋 Reference alternative (not in catalog)
AD7878KPZ-REEL
✅ Drop-In✓ In Stock
$17.6 / Unit
View Datasheet →AD7878AQ
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
AD7878SQ
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
AD7878JP
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
AD7878JPZ-REEL Maximum Ratings & Electrical Characteristics
| Manufacturer | Analog Devices Inc. |
| Part Number | AD7878JPZ-REEL |
| Resolution | 12 bit |
| Converter Type | SAR (Successive Approximation Register) |
| Number of Channels | 1 |
| Maximum Sample Rate | 100 kHz (kSamples/sec) |
| Nominal Sample Rate | 8.3 kSamples/sec |
| Track/Hold Acquisition Time | 2 us (typical) |
| Conversion Time | 7 us (typical) |
| Input Voltage Range | -3 V to +3 V (bipolar input, per third-party listing) |
| Supply Voltage (Analog) | +5 V |
| Supply Voltage (Negative) | -5 V to -3 V |
| Internal Reference | 3 V Zener reference |
| On-Chip FIFO | 8 words |
| Interface | DSP-compatible serial interface |
| Package | 28-pin PLCC (11.51 x 11.51 mm) |
| Operating Temperature | 0 C to +70 C |
| Screening Level | Commercial |
| Mounting Type | Surface Mount |
AD7878JPZ-REEL Pin Configuration
| Pin 1 | DGND — Digital ground |
| Pin 2 | DOUT — Serial data output |
| Pin 3 | SCLK — Serial clock input |
| Pin 4 | CONVST — Conversion start input |
| Pin 5 | CLKIN — Master clock input |
| Pin 6 | FSYNC — Frame synchronization |
| Pin 7 | BUSY — ADC busy status output |
| Pin 8 | VSS — Negative supply (-5 V to -3 V) |
| Pin 9 | AIN — Analog input (bipolar) |
| Pin 10 | AGND — Analog ground |
| Pin 11 | REF — Reference voltage (internal 3 V Zener) |
| Pin 12 | VDD — Positive supply (+5 V) |
| Pin 13 | NC — Not connected (per datasheet) |
| Pin 14 | NC — Not connected (per datasheet) |
| Pin 15 | NC — Not connected (per datasheet) |
| Pin 16 | NC — Not connected (per datasheet) |
| Pin 17 | NC — Not connected (per datasheet) |
| Pin 18 | NC — Not connected (per datasheet) |
| Pin 19 | NC — Not connected (per datasheet) |
| Pin 20 | NC — Not connected (per datasheet) |
| Pin 21 | NC — Not connected (per datasheet) |
| Pin 22 | NC — Not connected (per datasheet) |
| Pin 23 | NC — Not connected (per datasheet) |
| Pin 24 | NC — Not connected (per datasheet) |
| Pin 25 | NC — Not connected (per datasheet) |
| Pin 26 | NC — Not connected (per datasheet) |
| Pin 27 | NC — Not connected (per datasheet) |
| Pin 28 | VDD — Positive supply (+5 V) |
Typical Applications
AD7878JPZ-REEL is suitable for 6 applications: Process Control Data Acquisition, DSP Front-End Signal Chain, Multiplexed Data Acquisition Systems, Motor Control Position Feedback, Laboratory Instrumentation, Industrial Sensor Signal Conditioning.
Process Control Data Acquisition
The AD7878JPZ-REEL fits process-control front-ends where deterministic SAR conversion latency is required for closed-loop feedback. The 12-bit resolution (4096 codes) provides adequate precision for valve-position feedback, flow-rate measurement, and pressure-transducer signal chains after signal conditioning. With 100 kHz maximum throughput and 7 us conversion time, the part can multiplex several sensors via an external analog MUX while maintaining sub-millisecond loop latency. The internal 3 V Zener reference eliminates the need for a precision external reference, reducing BOM cost. The on-chip 8-word FIFO buffers conversion results so the PLC/DSP can batch-read multiple channels without missing samples, improving interrupt efficiency in industrial PLC platforms.
Recommended
DSP Front-End Signal Chain
The AD7878JPZ-REEL is purpose-built for DSP input signal chains in motor control, audio processing, and vibration analysis. The integrated DSP-compatible serial interface (CLKIN, CONVST, DOUT) connects directly to TI TMS320 and Analog Devices SHARC DSP serial ports with no glue logic. The 8-word FIFO decouples DSP interrupt service rate from ADC sample rate, allowing the processor to execute control algorithms between batch reads. With 100 kHz throughput the AD7878 can sample at the Nyquist rate for many audio-bandwidth signals (up to 50 kHz), and the SAR architecture provides deterministic latency critical for closed-loop control algorithms. Designers can use the FIFO to implement circular-buffer DMA transfers, offloading the CPU.
Recommended
Multiplexed Data Acquisition Systems
The AD7878JPZ-REEL's 100 kHz throughput, integrated track/hold, and 8-word FIFO make it well-suited for multiplexed data-acquisition systems where multiple sensor channels share a single ADC. A typical design pairs the AD7878 with an external analog multiplexer (e.g., ADG726) to scan 8/16 channels at per-channel rates up to 12.5 kHz. The SAR topology avoids the latency variations of sigma-delta ADCs, providing consistent per-channel timing for synchronized measurements. The internal reference simplifies calibration, and the bipolar ±3 V input range accepts signals directly from instrumentation amplifiers in industrial sensor bridges. The FIFO buffers samples between multiplexer channel switches, reducing host-processor interrupt load.
Recommended
Motor Control Position Feedback
The AD7878JPZ-REEL's deterministic SAR latency and 12-bit resolution make it suitable for motor-control position-feedback loops where encoder or resolver-derived analog signals must be digitized at high update rates. The 7 us conversion time supports sampling rates up to 100 kHz, far exceeding typical 10 kHz PWM cycle rates in field-oriented-control loops. The bipolar ±3 V input accepts direct signals from LVDT or resolver-to-digital converter front-ends. The on-chip FIFO allows the DSP/MCU to read multiple feedback samples per PWM cycle, supporting observers and Kalman-filter algorithms for sensorless control. The commercial 0-70 C temperature range suits industrial-indoor motor-drive enclosures.
Recommended
Laboratory Instrumentation
The AD7878JPZ-REEL is a strong choice for laboratory instrumentation including bench-top multimeters, signal analyzers, and educational laboratory equipment. The 12-bit resolution and 100 kHz throughput support general-purpose digitizing needs at the front end of bench instruments. The internal 3 V reference simplifies calibration procedures for educational and lab users who may not have precision external references on hand. The integrated FIFO and DSP-ready interface allow designers to interface directly with modern DSP or FPGA-based instrument controllers. The 28-pin PLCC package is suitable for through-hole-friendly prototyping using PLCC sockets, which is convenient for lab-iteration cycles and student lab environments.
Recommended
Industrial Sensor Signal Conditioning
The AD7878JPZ-REEL digitizes outputs from industrial sensors including strain gauges, thermocouple amplifiers, load cells, and pressure transducers in factory-automation and SCADA systems. The bipolar ±3 V input range accommodates typical instrumentation-amplifier outputs (e.g., AD620) without external level shifting. The 12-bit resolution provides 0.024% full-scale resolution, adequate for many industrial-sensor accuracy requirements. The internal reference and FIFO reduce external component count, helping meet strict industrial BOM-cost targets. The PLCC-28 package is rugged for industrial environments and accepts conformal coating for harsh factory-floor deployments per IEC 61010 industrial equipment standards.
Recommended
Recommended Products Summary
Engineering reference data for AD7878JPZ-REEL — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | AD7878JPZ | AD7878KPZ-REEL | AD7878AQ | AD7878SQ | AD7878JP |
|---|---|---|---|---|---|---|
| Package | 28-pin PLCC (11.51x11.51) | 28-pin PLCC (11.51x11.51) - same | 28-pin PLCC (11.51x11.51) - same | 28-pin PLCC (11.51x11.51) - same | 28-pin PLCC (11.51x11.51) - same | 28-pin PLCC (11.51x11.51) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Maximum Throughput | 100 kHz | 100 kHz | 100 kHz | 100 kHz | 100 kHz | 100 kHz |
| Temperature Grade | Commercial (0 C to +70 C) | Commercial (0 C to +70 C) | Industrial (extended) | Industrial (extended) | Military (-55 C to +125 C) | Commercial (0 C to +70 C) |
| Internal Reference | 3 V Zener | 3 V Zener | 3 V Zener | 3 V Zener | 3 V Zener | 3 V Zener |
| FIFO Depth | 8 words | 8 words | 8 words | 8 words | 8 words | 8 words |
Key Differentiators
- Integrated 8-word FIFO for batch DSP reads (vs AD7863ARZ-2REEL)
- Integrated 3 V Zener reference (vs AD7478AAKSZ-REEL)
- DSP-compatible serial interface (vs AD7707BRZ-REEL)
- PLCC-28 surface-mount footprint (vs AD7878BQ (CERDIP-28))
Design Notes
The AD7878JPZ-REEL requires both +5 V (VDD) and a negative supply (VSS between -5 V and -3 V) for the bipolar input stage. Decouple each supply pin with a 0.1 uF ceramic capacitor placed within 5 mm of the IC, plus a 10 uF tantalum bulk capacitor on each rail. The negative rail must be present and well-regulated; missing VSS will collapse the input common-mode range and may damage the input ESD structures. For single-supply systems, generate -5 V from a small switching inverter (e.g., ADP2301 in inverting configuration) or a charge pump. Estimated: total quiescent current draw is approximately 15-20 mA based on the AD7878 datasheet typical-power specification; verify with actual measurement in your design.
Place the AD7878JPZ-REEL PLCC-28 footprint on a 4-layer PCB with a continuous ground plane under the IC for thermal dissipation and EMI shielding. Keep analog input traces (AIN, REF) routed away from digital switching traces (CLKIN, CONVST, DOUT) to minimize digital-to-analog crosstalk. The PLCC-28 land pattern should follow JEDEC standard PLCC dimensions (JEDEC MS-018); verify the land pattern matches before PCB fabrication. Place the analog input RC filter (typically 100 ohm + 1 nF) close to the AIN pin to limit broadband noise; choose R/C values so the -3 dB cutoff is below 1 MHz to avoid degrading track/hold acquisition time (2 us typical).
Drive CLKIN with a clean low-jitter clock source (CMOS gate or DSP timer output) with rise/fall times below 10 ns to meet the SAR timing margin. Long clock traces should be terminated with a series resistor (33-47 ohm) close to the source to dampen reflections. The CONVST pulse width must satisfy the datasheet minimum (typically 30 ns); narrower pulses will not initiate conversion reliably. DOUT traces should be series-terminated and kept under 50 mm when driving capacitive loads above 10 pF (e.g., DSP serial-port input). For best EMI performance, route CLKIN and CONVST on inner layers between ground planes rather than top-layer microstrip.
Common pitfalls when using the AD7878JPZ-REEL include: (1) omitting the negative supply causes input common-mode collapse and incorrect conversions; (2) using a noisy or unstable clock on CLKIN introduces harmonic spurs in FFT plots; (3) bypassing the FIFO without reading it can cause overflow data loss - read DOUT at a rate >= sample rate to prevent FIFO overflow; (4) driving the bipolar AIN input beyond ±10 V without input clamping can damage the ESD diodes; (5) sharing the analog and digital grounds with a single trace instead of a star-ground topology introduces digital switching noise into the analog reference, degrading linearity. Always reference the AD7878 datasheet timing diagrams before PCB layout.
Compliance Information
RoHS compliance status not in the verified data provided. Per Analog Devices standard practice for AD7878 family, most plastic PLCC variants are RoHS-compliant, but this specific MPN's status should be confirmed with the manufacturer datasheet or product page.
