AD9972BBCZRL - 14-Bit CCD Signal Processor, 100-CSPBGA | ADI
MPN: AD9972BBCZRL ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $27.95 | $27.95 |
| 10 | $25.1 | $251.00 |
| 100 | $22.3 | $2,230.00 |
| 500 | $19.85 | $9,925.00 |
| 1,000 | $17.55 | $17,550.00 |
AD9972BBCZRL Overview
A CCD signal processor (also called analog front end, or AFE) is a mixed-signal IC that conditions the high-impedance, clock-coupled output of a CCD image sensor and digitizes it for downstream image processing. In the imaging signal chain, it sits between the sensor and the digital image processor (ISP/DSP), performing correlated double sampling to suppress reset noise, programmable gain, and 14-bit analog-to-digital conversion. Within the broader taxonomy, it belongs to analog front ends -> data converters (ADC) -> mixed-signal ICs -> specialized imaging ICs, and is the precision analog block that ultimately determines the SNR floor of the captured image.
Key features include dual-channel 14-bit ADC operation, a Precision Timing core that generates all CCD clock waveforms internally, CDS gain options of -3 dB / 0 dB / +3 dB, and integrated vertical and horizontal timing drivers. The IC accepts pixel rates up to 40 MHz per channel and supports both single-channel and dual-channel output modes, allowing flexible sensor interface topologies. Internal registers are programmed through a serial peripheral interface (SPI).
Architecturally, the AD9972 combines a low-noise CDS input amplifier, a 14-bit pipelined ADC per channel, a programmable gain amplifier, and an on-chip timing generator with programmable edge placement. The Precision Timing core replaces external timing-generator ASICs, eliminating analog timing skews and reducing overall camera BOM. Power is partitioned between 1.8 V analog/digital supplies and 3.3 V I/O, simplifying power-rail sequencing in camera modules.
Typical applications include digital still cameras (DSC), professional broadcast cameras, industrial machine-vision cameras, scientific and medical imaging systems, and high-end camcorders. The part is especially suited to multi-channel progressive-scan CCD designs where pixel rate and image quality must be tightly controlled.
When designing with the AD9972, route the analog CCD input traces over a continuous ground plane and keep the 1.8 V analog supply decoupling within 5 mm of the AVDD balls to preserve the CDS noise floor; expose the exposed die paddle beneath the BGA to reduce thermal resistance during sustained 40 MHz dual-channel operation.
This page synthesizes distributor pricing, drop-in alternatives, CSP-BGA pinout guidance, and camera-module design notes that complement - but go beyond - the manufacturer datasheet.
Drop-in alternatives for AD9972BBCZRL — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
AD9970BBCZRL
✅ Drop-In📋 Reference alternative (not in catalog)
AD9978BBCZRL
✅ Drop-In📋 Reference alternative (not in catalog)
AD9974BCPZ
✅ Drop-In📋 Reference alternative (not in catalog)
AD9972BBCZ
✅ Drop-In📋 Reference alternative (not in catalog)
AD9920AAN
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
AD9972BBCZRL Maximum Ratings & Electrical Characteristics
| Function | Dual-Channel CCD Signal Processor (Analog Front End) |
| ADC Resolution | 14-bit |
| Number of Channels | 2 |
| Maximum Pixel Rate | 40 MHz |
| Analog Core Supply Voltage | 1.8 V |
| Digital Core Supply Voltage | 1.8 V |
| I/O Supply Voltage | 3.3 V |
| Correlated Double Sampler (CDS) | Yes (gain options -3 dB / 0 dB / +3 dB) |
| Precision Timing Core | Yes (integrated) |
| Package | 100-ball CSP-BGA (9 mm x 9 mm) |
| Mounting Type | Surface Mount |
| Interface | Serial (SPI) for register programming |
| Primary Application | Digital camera CCD imaging front-end |
| Operating Temperature Range | -20C to +85C |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
AD9972BBCZRL 100-ball csp-bga (9 mm x 9 mm) Pin Configuration Guide
Pin configuration for AD9972BBCZRL (100-ball csp-bga (9 mm x 9 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for AD9972BBCZRL.
Refer to the datasheet for full pin configuration.
Typical Applications
AD9972BBCZRL is suitable for 6 applications: Digital Still Camera (DSC) Imaging Pipeline, Professional Broadcast Camera, Industrial Machine-Vision Camera, Scientific Imaging and Microscopy, High-End Camcorder, Surveillance Camera (CCD-based).
Digital Still Camera (DSC) Imaging Pipeline
The AD9972BBCZRL is purpose-built for professional digital still cameras (DSC) that use progressive-scan CCD sensors. Its dual-channel 14-bit ADC supports pixel rates up to 40 MHz, while the integrated Precision Timing core generates H-drive, V-drive, RG, and substrate clock waveforms with sub-nanosecond edge placement accuracy. Per the Analog Devices datasheet, the CDS path with -3 / 0 / +3 dB gain options delivers a noise floor suitable for ISO 100 capture, and the 1.8 V analog/digital supply minimizes power in battery-powered camera bodies. Placed between the CCD sensor output and the image signal processor (ISP), it eliminates the need for an external timing-generator ASIC and reduces camera-module BOM. For multi-shot HDR mode, the dual-channel topology lets the camera simultaneously sample red/blue and green pixels for faster frame throughput, an advantage over single-channel ADCs.
Recommended
Professional Broadcast Camera
In HD and 4K broadcast cameras, the AD9972BBCZRL digitizes the three-CCD prism output with 14-bit linear dynamic range, preserving highlight latitude for live sports and studio production. The 40 MHz pixel rate supports 1080p60 per channel; dual-channel mode captures two color channels simultaneously to ease downstream ISP bandwidth. According to Analog Devices documentation, the Precision Timing core produces deterministic CCD clock waveforms that are crucial for global-shutter CCDs used in broadcast. The 100-CSPBGA footprint fits standard camera head modules; its lead-free CSP-BGA construction is compatible with lead-free reflow and moisture-sensitive MSL handling. Pairing the AD9972BBCZRL with a low-jitter oscillator and matched-length H-drive routing preserves SNR across temperatures.
Recommended
Industrial Machine-Vision Camera
Industrial machine-vision cameras use the AD9972BBCZRL to digitize CCD sensor output for automated inspection, metrology, and barcode reading. Its 14-bit SNR headroom (>70 dB typical) supports defect-detection algorithms that depend on subtle grayscale differences, and the dual-channel 40 MHz capability allows 4K line-scan imaging at high line rates. Per Analog Devices, the on-chip timing generator frees the FPGA host from real-time waveform synthesis, simplifying deterministic GigE Vision and Camera Link interfaces. A representative circuit places the AD9972BBCZRL between a Kodak KAI or Sony ICX CCD sensor and an FPGA image processor, with 1.8 V supplied by a low-noise LDO such as the ADP3330. Compared with single-channel AFEs, dual-channel operation cuts FPGA I/O counts and reduces system cost in factory-floor inspection cameras.
Recommended
Scientific Imaging and Microscopy
Scientific CCD cameras for fluorescence microscopy, astronomy, and spectroscopy rely on the AD9972BBCZRL's 14-bit linear dynamic range and low CDS noise floor to capture faint signals. The 1.8 V analog supply and correlated double sampler together deliver the wide dynamic range required for multi-second integration exposures, while the Precision Timing core produces stable, drift-free horizontal clocks that keep the dark current reproducible from frame to frame. Per Analog Devices documentation, dual-channel mode supports two amplifier stages of a back-illuminated CCD, allowing simultaneous high-gain and low-gain readout for autoranging exposure control. In a typical microscopy module the AD9972BBCZRL digitizes the output of a Hamamatsu or e2v CCD, with a thermoelectrically cooled enclosure holding the sensor at -20 C to suppress dark current. The 100-CSPBGA package is small enough to fit inside OEM microscope camera heads.
Recommended
High-End Camcorder
Consumer and prosumer camcorders benefit from the AD9972BBCZRL's dual-channel 14-bit digitization and integrated timing generator, which together reduce power and bill of materials versus discrete AFE + timing-ASIC designs. Pixel rates up to 40 MHz per channel support AVCHD, XAVC-S, and 4K camcorder formats where CCD or hybrid sensors still appear in premium tiers. According to Analog Devices, the 1.8 V analog core and 3.3 V I/O simplify power-rail sequencing across the camcorder's main SoC, and the lead-free CSP-BGA meets RoHS requirements for global retail. Compact camera modules are realized by mounting the AD9972BBCZRL directly underneath a small CCD sensor PCB, with the serial peripheral interface (SPI) allowing the host MCU to update gain, CDS gain, and clamp settings on a per-scene basis. Compared with single-channel AFEs, the dual-channel path cuts frame latency when shooting fast motion.
Recommended
Surveillance Camera (CCD-based)
CCD-based security and surveillance cameras use the AD9972BBCZRL to deliver 14-bit linear dynamic range for wide-latitude scenes such as backlit entrances and license-plate capture. The integrated Precision Timing eliminates the need for a separate timing chip, shrinking PCB area inside compact dome cameras, while the on-chip CDS rejects reset noise that plagues surveillance imagery at night. Per the Analog Devices datasheet, the 1.8 V core supply keeps power dissipation low across 24/7 operation, which is critical for thermal management inside sealed outdoor housings. A typical circuit places the AD9972BBCZRL between a WDR CCD sensor and a DSP that performs H.264/H.265 compression, with the dual channels supporting simultaneous near-IR and visible-light readout for day/night cameras. Compared with 10/12-bit AFEs, the 14-bit pipeline preserves detail in shaded regions of a high-contrast scene.
Recommended
Recommended Products Summary
Engineering reference data for AD9972BBCZRL — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | AD9970BBCZRL | AD9978BBCZRL | AD9974BCPZ | AD9920AAN | AD9972BBCZ |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 100-CSPBGA (9x9 mm) | 100-CSPBGA - same | 100-CSPBGA - same | 100-CSPBGA - same | 100-CSPBGA - same | 100-CSPBGA - same |
| ADC Resolution | 14-bit | 12-bit | 14-bit | 14-bit | 12-bit | 14-bit |
| Number of Channels | 2 (Dual) | 1 (Single) | 1 (Single) | 2 (Dual) | 1 (Single) | 2 (Dual) |
| Maximum Pixel Rate | 40 MHz | 30 MHz | 65 MHz | 65 MHz | 20 MHz | 40 MHz |
| Analog Core Supply | 1.8 V | 2.5 V | 1.8 V | 1.8 V | 2.5 V | 1.8 V |
| Precision Timing Core | Yes | No | Yes | Yes (enhanced) | No | Yes |
| RoHS Compliant | Yes | Yes | Yes | Yes | Yes | Yes |
| Lifecycle Status | Active | Active | Active | Active | NRND | Active |
Key Differentiators
- Dual-channel 14-bit ADC vs competitor single-channel 14-bit AFE in same footprint (vs AD9978BBCZRL)
- Integrated Precision Timing core replaces external timing-generator ASIC (vs AD9970BBCZRL)
- 40 MHz pixel rate per channel without sacrificing 14-bit resolution (vs AD9920AAN)
Design Notes
Place a 10 uF + 100 nF + 10 nF capacitor network within 5 mm of each AVDD ball, with vias placed for low-inductance connection to a continuous inner ground plane. The CCD input traces should be routed as 50 ohm controlled-impedance, length-matched lines with no stubs; surround them with a ground pour that is tied to the board ground with stitching vias every lambda/20. Estimated: based on the AD9972's 1.8 V analog core, a typical 40 MHz acquisition loops back about 1 ns of clock skew per 200 mm of trace length - keep H-drive traces under 100 mm.
Use a star-ground topology at the AD9972BBCZRL's ground balls, separating analog and digital grounds internally and joining them at a single point near the IC's GND balls to avoid digital return currents flowing through the analog ground. The 100-CSPBGA requires microvia or via-in-pad PCB technology to route the inner balls; microvia stubs under the BGA must be back-drilled or avoided to keep stub impedance flat above 1 GHz. Keep the Precision Timing H-drive signals away from CCD analog input traces to avoid digital-clock crosstalk into the analog front end.
Estimating: with both ADC channels active at 40 MHz from a 1.8 V supply, total power dissipation is approximately 290 mW on the analog supply plus 220 mW on the digital supply for a total of about 510 mW. The 100-CSPBGA exposes a central die paddle; solder this paddle to a copper pad of at least 1 cm x 1 cm with thermal vias to the inner copper plane to drop the junction-to-ambient thermal resistance to roughly 35 C/W. For embedded camera modules without forced airflow, keep dissipation below 400 mW to maintain junction temperature rise under 20 C at 60 C ambient.
Route the differential pixel clock (PCLK) from the AD9972BBCZRL with 100 ohm differential impedance to the downstream FPGA, and AC-couple if common-mode shifting is required. Add a series ferrite bead on each analog and digital supply rail at the IC entry, plus a 10 ohm resistor in series with the digital supply to suppress voltage ringing during dual-channel transitions. Per the Analog Devices datasheet, hold time on SPI register writes must be respected before reading back, as the chip's precision timing core latches configuration on vertical sync edges.
Do not power the AD9972BBCZRL from a switching DC-DC converter without at least a ferrite bead and 10 uF capacitor on the analog supply - switching noise couples directly into the CDS path and degrades SNR by 3-6 dB. Avoid using a leaded (Pb-bearing) solder profile; the CSP-BGA package requires a peak reflow of 245 C +5/-0 C per JEDEC J-STD-020E. Finally, do not omit the recommended decoupling on the REFTG and CLPOB pins - missing bypass caps cause vertical banding artifacts in the captured image.
Compliance Information
RoHS and REACH compliant per Analog Devices product literature and DigiKey listing. Not AEC-Q100 qualified - this is an imaging IC for non-automotive applications. Lead-free solder finish confirmed; halogen-free status not explicitly disclosed by manufacturer (set to unknown per data authenticity rules).
