ADC1002S020HL/C1:1 - 10-bit 20MSPS Video ADC, 32-LQFP | Renesas
MPN: ADC1002S020HL/C1:1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.45 | $8.45 |
| 10 | $7.62 | $76.20 |
| 100 | $6.41 | $641.00 |
| 500 | $5.18 | $2,590.00 |
| 1,000 | $4.27 | $4,270.00 |
ADC1002S020HL/C1:1 Overview
What is a pipelined ADC? A pipelined Analog-to-Digital Converter is a type of high-speed ADC that uses multiple cascaded low-resolution stages to convert an analog signal into digital code. Each stage samples the input, performs a coarse conversion, and passes the residue to the next stage, enabling simultaneous sampling and conversion that achieves sampling rates from a few MHz up to hundreds of MHz. Pipelined ADCs sit within the broader hierarchy of ADC -> data converter -> mixed-signal IC -> semiconductor, and are widely preferred for video, imaging, communications, and instrumentation where speed and resolution must coexist.
The ADC1002S020 features a differential analog input, a parallel CMOS digital interface, and a standby mode that reduces device power consumption when conversions are not required. Its architecture supports sampling rates up to 20 MSPS, making it well matched to standard-definition video digitisation, CCD imaging front-ends, and IF-sampling communications receivers. The single 5.25 V supply simplifies power-tree design versus parts that require separate analog and digital rails.
Technically, the part uses a resistive-ladder DAC and pipelined quantizer topology, providing 10-bit linearity for video-grade applications. Operating temperature spans -20C to +75C (commercial grade), suiting indoor equipment, test instruments, and embedded video capture modules. The CMOS-compatible parallel interface simplifies connection to FPGAs, ASICs, and DSPs without level translation.
Typical applications include professional video digitizers, CCD/CIS imaging front-ends, IF-stage digitizers in communications receivers, ultrasound beamforming preprocessing, and general-purpose high-speed data acquisition systems. The 32-LQFP footprint is widely accepted on standard 4-layer PCB stacks with no exotic routing. When designing with this part, ensure the analog input is bandwidth-limited to meet Nyquist criteria at 20 MSPS, decouple AVDD and DVDD with separate 100 nF + 10 uF networks near the pins, and avoid running digital switching traces under the analog input pin to preserve SNR.
Drop-in alternatives for ADC1002S020HL/C1:1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC1002S020HL/C1:1 (same form factor and footprint) — differing in Input Type, Package, Data Interface, Architecture, Sampling Rate.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC1002S020HL/C1
✅ Drop-In✓ In Stock
$2.96 / Unit
View Datasheet →ADC1002S030HL
✅ Drop-In📋 Reference alternative (not in catalog)
ADC1003S020HL
✅ Drop-In📋 Reference alternative (not in catalog)
ADC1002S020HL/C1:1 Maximum Ratings & Electrical Characteristics
| Resolution | 10 bits |
| Number of ADC Channels | 1 |
| Sampling Rate | 20 MSPS (max) |
| Architecture | Pipelined |
| Input Type | Differential |
| Data Interface | Parallel (CMOS) |
| Supply Voltage (Analog) | 3.0 V to 5.25 V |
| Supply Voltage (Digital) | 3.0 V to 5.25 V |
| Package | 32-LQFP (5 x 5 mm, SOT401-1) |
| Mounting Type | Surface Mount |
| Operating Temperature | -20 C to +75 C |
| Packaging | Tape & Reel (TR) |
| Standby Mode | Yes (low-power) |
| Terminal Form | Gull Wing |
| Terminal Count | 32 |
ADC1002S020HL/C1:1 Pin Configuration
| Pin 1 | AVCC — Analog supply voltage |
| Pin 2 | AGND — Analog ground |
| Pin 3 | IN+ — Differential analog input (positive) |
| Pin 4 | IN- — Differential analog input (negative) |
| Pin 5 | AVCC — Analog supply voltage |
| Pin 6 | AGND — Analog ground |
| Pin 7 | VREF — Voltage reference |
| Pin 8 | AGND — Analog ground |
| Pin 9 | OE — Output enable (active high) |
| Pin 10 | CLK — Conversion clock input |
| Pin 11 | DVCC — Digital supply voltage |
| Pin 12 | DGND — Digital ground |
| Pin 13 | D9 — Data output bit 9 (MSB) |
| Pin 14 | D8 — Data output bit 8 |
| Pin 15 | D7 — Data output bit 7 |
| Pin 16 | D6 — Data output bit 6 |
| Pin 17 | D5 — Data output bit 5 |
| Pin 18 | D4 — Data output bit 4 |
| Pin 19 | D3 — Data output bit 3 |
| Pin 20 | D2 — Data output bit 2 |
| Pin 21 | D1 — Data output bit 1 |
| Pin 22 | D0 — Data output bit 0 (LSB) |
| Pin 23 | DGND — Digital ground |
| Pin 24 | DVCC — Digital supply voltage |
| Pin 25 | STBY — Standby mode control |
| Pin 26 | NC — Not connected (per datasheet) |
| Pin 27 | AVCC — Analog supply voltage |
| Pin 28 | AGND — Analog ground |
| Pin 29 | AVCC — Analog supply voltage |
| Pin 30 | AGND — Analog ground |
| Pin 31 | AVCC — Analog supply voltage |
| Pin 32 | AGND — Analog ground |
Typical Applications
ADC1002S020HL/C1:1 is suitable for 6 applications: Standard-Definition Video Digitisation, CCD / CIS Imaging Front-End, IF-Stage Digitisation in Communications Receivers, Industrial Ultrasound Beamforming Preprocessing, High-Speed Data Acquisition Modules, Test & Measurement Instrumentation.
Standard-Definition Video Digitisation
The ADC1002S020HL/C1:1 fits SD video capture front-ends because its 20 MSPS sampling rate comfortably covers CIF/SIF resolutions and its 10-bit depth delivers sufficient dynamic range for broadcast-quality imagery. Placed immediately after a video amplifier and anti-alias filter, the differential analog input rejects common-mode noise from long cable runs while the parallel CMOS output drives an FPGA or DSP without latency. Compared to higher-speed alternatives, the 20 MSPS rate keeps power dissipation low - critical for multi-channel camera modules. Renesas design notes recommend placing 100 nF + 10 uF decoupling networks near AVDD and DVDD and avoiding digital switching traces under the analog input pin.
Recommended
CCD / CIS Imaging Front-End
For CCD and CMOS Image Sensor front-ends, the ADC1002S020HL/C1:1 provides 10-bit pixel-level conversion at up to 20 MSPS, matching typical line-scan imaging rates. The differential analog input pairs cleanly with correlated double-sampling (CDS) circuits and the parallel output synchronises with the sensor's pixel clock without buffering. The single 3.0-5.25 V supply simplifies power distribution in compact camera modules, and the integrated standby mode reduces power when the sensor is not actively capturing. Per the Renesas datasheet, designers should clock the ADC at the same rate as the pixel clock to maintain sample alignment.
Recommended
IF-Stage Digitisation in Communications Receivers
The ADC1002S020HL/C1:1 is well-suited to IF-sampling in narrowband communications receivers where the intermediate frequency sits below 10 MHz. The 20 MSPS rate comfortably satisfies Nyquist for IFs up to ~9 MHz, and the 10-bit resolution delivers adequate SNR for demodulation in cost-sensitive radio designs. Its differential analog input improves common-mode rejection of IF coupling-network noise, while the CMOS parallel output interfaces directly with baseband DSPs. The single 5 V (or 3.3 V) supply aligns with the receiver's main power rail. Per Renesas datasheet guidance, use an input transformer or differential driver to maximise second-order distortion performance.
Recommended
Industrial Ultrasound Beamforming Preprocessing
Lower-end ultrasound beamforming systems use the ADC1002S020HL/C1:1 as a low-cost per-channel digitiser for analog front-end signals below 20 MHz. Its 10-bit resolution is sufficient for B-mode imaging at moderate depths, and its parallel output enables channel-to-channel synchronisation critical for beamforming coherence. The 32-LQFP footprint allows compact multi-channel PCB layouts and the 5 V analog supply simplifies integration with analog receive chains. Compared to higher-resolution ultrasound ADCs (AD9226, AD9245), the 10-bit depth trades dynamic range for substantial cost savings in budget-sensitive medical and industrial imaging systems.
Recommended
High-Speed Data Acquisition Modules
General-purpose DAQ modules targeting 20 MHz bandwidth use the ADC1002S020HL/C1:1 for cost-effective single-channel digitisation. The pipelined architecture delivers consistent sample latency, simplifying trigger alignment with downstream DSP, while the parallel CMOS output allows direct FPGA connection at full rate. Operating from a single 3.3 V or 5 V rail, the ADC simplifies mixed-signal power-tree design in space-constrained modules. The commercial -20C to +75C temperature range suits laboratory and industrial environments, but the part is not qualified for automotive AEC-Q100 applications - pair with a Renesas automotive-grade equivalent if needed.
Recommended
Test & Measurement Instrumentation
Bench-top instruments such as digital oscilloscope front-ends and arbitrary waveform digitiser cards leverage the ADC1002S020HL/C1:1 for low-cost 10-bit, 20 MSPS capture. The pipelined core provides uniform aperture delay across samples, simplifying time-domain measurements, and the parallel CMOS output interfaces directly with FPGA-based acquisition memory. Single 3.3-5 V supply operation enables integration into USB-powered test instruments without complex power sequencing. Compared to oscilloscope-grade ADCs (e.g., ADS6129 at 80 MSPS), the 10-bit depth limits dynamic range but delivers substantial cost savings for budget-sensitive measurement tools where 10-bit ENOB is adequate.
Recommended
Recommended Products Summary
Engineering reference data for ADC1002S020HL/C1:1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC1002S020HL/C1 | ADC1002S030HL | ADC1003S020HL |
|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 32-LQFP (5x5 mm) | 32-LQFP (5x5 mm) - same | 32-LQFP (5x5 mm) - same | 32-LQFP (5x5 mm) - same |
| Resolution | 10 bits | 10 bits | 10 bits | 10 bits |
| Sampling Rate | 20 MSPS | 20 MSPS | 30 MSPS | 20 MSPS |
| Supply Voltage | 3.0 V to 5.25 V | 3.0 V to 5.25 V | 3.0 V to 5.25 V | 3.0 V to 5.25 V |
| Input Type | Differential | Differential | Differential | Differential |
| Operating Temperature | -20 C to +75 C | -20 C to +75 C | -20 C to +75 C | -20 C to +75 C |
| Standby Mode | Yes | Yes | Yes | Yes |
Key Differentiators
- Single 3.0-5.25 V supply simplifies power-tree design vs multi-rail ADC competitors (vs ADC1002S030HL)
- Integrated standby mode reduces power consumption when conversions are idle (vs ADC1003S020HL)
- Pipelined core delivers uniform sample-to-sample latency for synchronised capture (vs ADC1002S020HL/C1)
Design Notes
Use separate analog and digital supply rails with ferrite-bead isolation, and decouple AVDD and DVDD near the IC pins with a 100 nF ceramic in parallel with a 10 uF tantalum or polymer. The single 3.0-5.25 V supply supports both analog and digital domains; routing them as separate planes with a ferrite bead between domains prevents digital switching noise from corrupting the analog input.
Route the analog differential input pair (IN+, IN-) as a matched 100 ohm differential microstrip, kept short and away from digital output buses. Place the input anti-alias filter within 5 mm of the IN+/IN- pins and avoid routing any digital switching traces (D0-D9, CLK, OE) under the analog input or reference area. Solid analog and digital ground planes with a single connection point near the IC prevent ground-loop noise injection.
Clock the ADC1002S020HL/C1:1 with a low-jitter CMOS clock source; jitter above 10 ps rms will degrade SNR at 20 MSPS Nyquist input. Keep the CLK trace impedance-controlled to 50 ohm and terminate close to the IC if trace length exceeds 25 mm. Series-terminate the digital output bits D0-D9 with 33 ohm resistors if driving long traces to an FPGA.
Compliance Information
RoHS and REACH compliant per Renesas/NXP product page. Not AEC-Q100 qualified - commercial grade only. Lead-free terminations. Halogen-free status not explicitly stated in available data.
