ADC1213D065HN-C1 - Dual 12-bit 65 MSPS ADC, JESD204A | Renesas
MPN: ADC1213D065HN-C1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.95 | $2,895.00 |
| 500 | $24.8 | $12,400.00 |
| 1,000 | $21.5 | $21,500.00 |
ADC1213D065HN-C1 Overview
What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed sampling architecture that processes the analog input through a cascade of low-resolution flash stages, each stage producing a digital residue passed to the next. Pipelined ADCs sit in the hierarchy of data converters -> Nyquist-rate ADC -> flash and pipelined architectures -> high-speed data acquisition ICs. They deliver the best trade-off between sample rate, resolution, and power for communications and imaging bandwidths, typically 10 MSPS to 500 MSPS at 8-14 bits.
The ADC1213D family is optimized for high dynamic performance and low power, making it ideal for driving downstream FPGAs or DSPs over the JESD204A serial link. Each channel includes its own track-and-hold amplifier, allowing simultaneous sampling of two analog signals without skew. The device operates from a single 1.8 V supply and supports LVDS-compatible clock inputs.
Key differentiating features include 65 MSPS guaranteed sampling rate per channel, dual simultaneous sampling, 12-bit resolution, JESD204A serial output for reduced pin count and simplified board routing, and integrated input buffers that relax external driver requirements. The device is specified over the -40C to +85C extended industrial temperature range and is lead-free / RoHS compliant.
Typical applications include multi-carrier wireless base-station receivers, medical imaging systems such as ultrasound beamformers, radar and lidar signal processing, portable test and measurement instrumentation, and dual-channel data acquisition cards. The wide input bandwidth and excellent spurious-free dynamic range make it suitable for direct-IF sampling at intermediate frequencies up to 200 MHz.
Designers should consider that the JESD204A interface requires careful PCB layout with controlled-impedance differential traces and that the device's input common-mode voltage must be set externally. The exposed thermal pad (EP) must be soldered to the ground plane for proper heat dissipation and electrical performance.
This page synthesizes distributor pricing, drop-in alternatives, application context, and design guidance not aggregated elsewhere, supporting faster component selection for high-speed dual-channel data acquisition systems.
Drop-in alternatives for ADC1213D065HN-C1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC1213D065HN-C1 (same form factor and footprint) — differing in Package, Input Type, Number of Channels, Resolution, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC1213D080HN/C1
✅ Drop-In📋 Reference alternative (not in catalog)
ADC1213D105HN/C1
✅ Drop-In📋 Reference alternative (not in catalog)
ADC1213D125HN/C1
✅ Drop-In📋 Reference alternative (not in catalog)
ADC1210S065HN/C1
✅ Drop-In✓ In Stock
$8.4 / Unit
View Datasheet →ADC1015S125HN/C1
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →ADC1012D080HN/C1:5
✅ Drop-In✓ In Stock
$12.1 / Unit
View Datasheet →ADC1213D065HN-C1 Maximum Ratings & Electrical Characteristics
| Number of Channels | 2 (simultaneous sampling) |
| Resolution | 12 bit |
| Sample Rate (per channel) | 65 MSPS |
| Architecture | Pipelined |
| Input Type | Single-ended / differential (with input buffer) |
| Output Interface | Serial JESD204A (1 lane) |
| Supply Voltage | 1.8 V |
| Operating Temperature | -40C to +85C |
| Package | 56-VFQFPN-EP (HVQFN), 8x8 mm |
| Mounting Type | Surface Mount |
| MSL Level | 3 |
| RoHS Status | Compliant |
| Lead-Free | Yes |
ADC1213D065HN-C1 56-vfqfpn-ep (hvqfn), 8x8 mm Pin Configuration Guide
Pin configuration for ADC1213D065HN-C1 (56-vfqfpn-ep (hvqfn), 8x8 mm package). This analog component features input, output, and power supply pins. Refer to the manufacturer datasheet for offset null, compensation, and enable pin configurations. Ideal for signal conditioning and amplifier circuits.
No detailed pinout data available for ADC1213D065HN-C1.
Refer to the datasheet for full pin configuration.
Typical Applications
ADC1213D065HN-C1 is suitable for 7 applications: Wireless Base Station Receiver, Medical Ultrasound Beamforming, Radar and Lidar Digitization, Portable Test and Measurement, Software-Defined Radio (SDR), Dual-Channel Data Acquisition Card, Communications Test Equipment.
Wireless Base Station Receiver
The ADC1213D065HN-C1 is well-suited for multi-carrier wireless base-station receivers requiring dual-channel simultaneous sampling of I/Q signals. Its 65 MSPS per channel rate supports direct-IF sampling of WCDMA and LTE signals with intermediate frequencies up to 200 MHz, while the dual simultaneous track-and-hold eliminates inter-channel skew critical for I/Q demodulation. The JESD204A serial output reduces FPGA pin count and simplifies board routing. The 1.8 V supply and ~250 mW per channel power consumption suit compact remote-radio-head (RRH) designs where thermal budget is constrained.
Recommended
Medical Ultrasound Beamforming
In medical ultrasound systems, the ADC1213D065HN-C1's dual simultaneous-sampling architecture supports 2-channel per-chip digitization of transducer array signals. The 65 MSPS rate is sufficient for imaging at typical 5-15 MHz ultrasound frequencies with adequate oversampling for harmonic imaging. The integrated input buffer eliminates the need for an external ADC driver op-amp, reducing board space and BOM cost per channel. The JESD204A output streams samples directly to an FPGA beamformer over a high-speed serial link, replacing parallel LVDS buses that consume 24+ pins per ADC.
Recommended
Radar and Lidar Digitization
The ADC1213D065HN-C1's dual simultaneous sampling makes it appropriate for radar and lidar digitizer front-ends, where two channels of return-signal data must be captured with deterministic phase relationship. The 65 MSPS per channel rate supports baseband digitization of short-range automotive radar and industrial lidar returns. The 12-bit resolution provides 72 dB dynamic range, adequate for distinguishing target returns from clutter. The JESD204A interface connects to FPGAs implementing CFAR detection and angle-of-arrival algorithms without consuming excessive board space or routing complexity.
Recommended
Portable Test and Measurement
Portable test and measurement instruments such as handheld oscilloscopes, spectrum analyzers, and bench-top data loggers benefit from the ADC1213D065HN-C1's low power consumption and dual-channel density. The 1.8 V supply and small 8x8 mm QFN-EP package suit battery-powered designs, while the 65 MSPS rate captures signals up to 30 MHz with sufficient oversampling for accurate reconstruction. The integrated input buffer simplifies front-end design and reduces external component count. The JESD204A output to a low-cost FPGA enables flexible trigger and measurement logic in the digital domain.
Recommended
Software-Defined Radio (SDR)
The ADC1213D065HN-C1's dual-channel architecture is ideal for SDR I/Q digitization, where two channels of in-phase and quadrature data must be sampled synchronously. The 65 MSPS rate supports HF, VHF, and low-UHF receiver designs with analog bandwidth up to 30 MHz. The JESD204A serial output connects directly to FPGA-based DDC (digital down-converter) implementations. The 12-bit resolution and pipelined architecture provide the spurious-free dynamic range needed to distinguish weak signals in the presence of strong adjacent-channel interferers typical of crowded HF bands.
Recommended
Dual-Channel Data Acquisition Card
PCIe and PXIe data acquisition cards requiring simultaneous sampling on two channels use the ADC1213D065HN-C1 to minimize per-channel cost and power while preserving high dynamic range. The 65 MSPS rate captures transient signals and fast-slewing waveforms in industrial and scientific applications. The JESD204A interface streams data to a PCIe FPGA bridge over a single high-speed serial lane, freeing FPGA pins for memory and host-interface logic. The exposed thermal pad (EP) supports high-density multi-ADC boards where heat must be conducted into the chassis.
Recommended
Communications Test Equipment
Manufacturing test equipment for cellular handsets, Wi-Fi modules, and Bluetooth devices uses the ADC1213D065HN-C1 for production-line RF signal analysis. The dual channel supports simultaneous TX and RX measurements, or two-port vector network analysis. The 65 MSPS rate handles modulation bandwidths of Wi-Fi 5/6 and 4G LTE signals. The JESD204A interface integrates with FPGA-based real-time signal processing for pass/fail decisions within production cycle-time budgets. The 56-VFQFPN-EP package supports high-density ATE pin-electronics boards.
Recommended
Recommended Products Summary
Engineering reference data for ADC1213D065HN-C1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC1213D080HN/C1 | ADC1213D105HN/C1 | ADC1213D125HN/C1 | ADC1210S065HN/C1 | ADC1015S125HN/C1 |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 56-VFQFPN-EP (8x8 mm) | 56-VFQFPN-EP (8x8 mm) - same | 56-VFQFPN-EP (8x8 mm) - same | 56-VFQFPN-EP (8x8 mm) - same | 56-VFQFPN-EP (8x8 mm) - same | 56-VFQFPN-EP (8x8 mm) - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 10 bit |
| Number of Channels | 2 | 2 | 2 | 2 | 1 | 1 |
| Sample Rate | 65 MSPS | 80 MSPS | 105 MSPS | 125 MSPS | 65 MSPS | 125 MSPS |
| Output Interface | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Key Differentiators
- Lowest cost 12-bit dual 65 MSPS JESD204A ADC in family (vs ADC1213D105HN/C1)
- Dual simultaneous sampling eliminates I/Q skew (vs ADC1010S080HN/C1:5)
- JESD204A serial interface reduces FPGA pin count (vs Parallel LVDS ADCs)
Design Notes
The JESD204A serial link from the ADC1213D065HN-C1 to the FPGA requires controlled-impedance differential routing (typically 100 ohm differential) with matched lengths to within a few millimeters. Use a continuous ground reference plane beneath the serial traces to maintain impedance. Length matching is more critical than absolute length for this 1.8 V CML interface. Avoid routing near noisy digital signals or switching power supplies.
The 56-VFQFPN-EP package has an exposed thermal pad that must be soldered to a solid ground plane for both electrical performance and heat dissipation. Use an array of thermal vias (0.3 mm drill, 1.0 mm pitch) under the EP to conduct heat to inner ground planes. Insufficient via count or no EP soldering will cause the device to overheat at high sample rates and degrade SNR performance.
The ADC1213D065HN-C1's clock input is highly sensitive to jitter, which directly degrades SNR at high analog input frequencies. Use an ultra-low-jitter clock source (typically < 200 fs RMS jitter) and route the clock signal with a clean ground reference, keeping it away from noisy digital traces. SNR degrades proportionally to log(fin) for input frequencies above 50 MHz, so clock jitter is the dominant SNR-limiting factor for wideband applications.
The ADC1213D065HN-C1 requires a low-noise 1.8 V supply with at least 20 mV peak-to-peak ripple tolerance. Place 10 uF bulk ceramic capacitors and 0.1 uF decoupling capacitors close to each supply pin. Star-ground the analog and digital 1.8 V returns to avoid ground loops. A ferrite bead on the digital 1.8 V supply can reduce digital switching noise coupling into the analog domain.
Do not exceed the maximum analog input voltage range, which is centered around the common-mode voltage (typically 0.9 V for 1.8 V supply). The input common-mode voltage must be set externally by the driver op-amp, not by the ADC. Also, the JESD204A link parameters (L, M, F, K) must be programmed via SPI/serial configuration before the link will establish; consult the Renesas datasheet for the correct values for your desired sample rate and lane count.
Compliance Information
RoHS compliant per Renesas product page and distributor listings. Operating temperature range -40C to +85C is extended industrial grade; AEC-Q100 automotive qualification is not specified. The C1 suffix denotes 65 MSPS speed grade.
