ADC1210S065HN/C1 - 12-bit 65 MSPS ADC, LVDS/CMOS, HVQFN-40 | Renesas
MPN: ADC1210S065HN/C1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.45 | $114.50 |
| 100 | $10.07 | $1,007.00 |
| 500 | $9.25 | $4,625.00 |
| 1,000 | $8.4 | $8,400.00 |
ADC1210S065HN/C1 Overview
An ADC (Analog-to-Digital Converter) is a data acquisition integrated circuit that converts continuous analog input signals into discrete digital codes at a defined sampling rate, sitting at the boundary between the analog front end and the digital signal chain within a data acquisition system. Pipelined ADCs like the ADC1210S use multiple low-resolution flash stages to deliver high sample rates (tens to hundreds of MSPS) at moderate resolution (8-14 bits), making them the workhorse of communications, imaging, and test-and-measurement equipment where bandwidth, not absolute DC linearity, is the primary requirement.
The ADC1210S065HN/C1 features 12-bit resolution, a 65 MSPS maximum sampling rate, selectable CMOS or LVDS DDR output modes, and an internal reference, reducing the bill of materials for typical system designs. The HVQFN-40 package provides an exposed thermal pad for low thermal resistance, which is critical for industrial-grade continuous sampling. Operating from a single 1.8 V analog supply and a separate 1.8 V or 3.3 V digital output supply, the device simplifies multi-rail system design. The 12-bit linearity and SNR are tuned for IF-sampling and high-speed instrumentation use cases.
Typical applications include communications IF/baseband digitization, industrial imaging and machine vision, ultrasound receive-channel front ends, portable oscilloscopes and digitizers, and software-defined radio. When designing with this device, place the analog input network (transformer or differential driver) within 5 mm of the input pins and provide a solid ground pour stitched with vias around the exposed pad to keep the SNR within datasheet limits. Match LVDS output trace lengths (within 5 mil) for the DDR clock and data pairs to preserve timing margins.
Drop-in alternatives for ADC1210S065HN/C1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC1210S065HN/C1 (same form factor and footprint) — differing in Package, Input Type, Number of Channels, Resolution, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC1210S080HN/C1:5
✅ Drop-In📋 Reference alternative (not in catalog)
ADC1210S105HN/C1:5
✅ Drop-In✓ In Stock
$13.33 / Unit
View Datasheet →ADC1210S125HN/C1:5
✅ Drop-In✓ In Stock
$21.1 / Unit
View Datasheet →ADC1015S125HN/C1:5
✅ Drop-In📋 Reference alternative (not in catalog)
ADC1010S080HN/C1:5
✅ Drop-In✓ In Stock
$7.32 / Unit
View Datasheet →ADC1012D080HN/C1:5
✅ Drop-In✓ In Stock
$12.1 / Unit
View Datasheet →ADC1112D125HN-C18
✅ Drop-In✓ In Stock
$9.48 / Unit
View Datasheet →ADC1210S065HN/C1 Maximum Ratings & Electrical Characteristics
| Resolution | 12 bit |
| Number of Channels | 1 |
| Sampling Rate | 65 MSPS (max) |
| Architecture | Pipelined |
| Input Type | Differential (single-ended capable via T-network) |
| Digital Output Interface | CMOS or LVDS DDR (selectable) |
| Analog Supply Voltage | 1.8 V (typ.) |
| Digital Output Supply Voltage | 1.8 V or 3.3 V |
| Reference Type | Internal (external optional) |
| Operating Temperature Range | -40 C to +85 C (industrial) |
| Package | HVQFN-40, 6 x 6 mm, 0.85 mm height |
| Package Code (JEDEC) | SOT618-1 (MO-220) |
| Mounting Type | Surface Mount |
| Screening Level | Industrial |
| RoHS Status | Compliant |
ADC1210S065HN/C1 Pin Configuration
| Pin 1 | VA — Analog 1.8V supply |
| Pin 2 | GND — Ground |
| Pin 3 | IN+ — Differential analog input (positive) |
| Pin 4 | IN- — Differential analog input (negative) |
| Pin 5 | VCM — Common-mode output voltage for input biasing |
| Pin 6 | VA — Analog 1.8V supply |
| Pin 7 | GND — Ground |
| Pin 8 | VA — Analog 1.8V supply |
| Pin 9 | GND — Ground |
| Pin 10 | CLK+ — Differential clock input (positive) |
| Pin 11 | CLK- — Differential clock input (negative) |
| Pin 12 | GND — Ground |
| Pin 13 | VA — Analog 1.8V supply |
| Pin 14 | GND — Ground |
| Pin 15 | D11 — LVDS/CMOS data output bit 11 (MSB) |
| Pin 16 | D10 — LVDS/CMOS data output bit 10 |
| Pin 17 | D9 — LVDS/CMOS data output bit 9 |
| Pin 18 | D8 — LVDS/CMOS data output bit 8 |
| Pin 19 | VDR — Digital output supply (1.8V or 3.3V) |
| Pin 20 | GND — Ground |
| Pin 21 | D7 — LVDS/CMOS data output bit 7 |
| Pin 22 | D6 — LVDS/CMOS data output bit 6 |
| Pin 23 | D5 — LVDS/CMOS data output bit 5 |
| Pin 24 | D4 — LVDS/CMOS data output bit 4 |
| Pin 25 | D3 — LVDS/CMOS data output bit 3 |
| Pin 26 | D2 — LVDS/CMOS data output bit 2 |
| Pin 27 | D1 — LVDS/CMOS data output bit 1 |
| Pin 28 | D0 — LVDS/CMOS data output bit 0 (LSB) |
| Pin 29 | VDR — Digital output supply (1.8V or 3.3V) |
| Pin 30 | GND — Ground |
| Pin 31 | DOR — Data out-of-range indicator |
| Pin 32 | OE — Output enable (active high) |
| Pin 33 | PD — Power-down (active high) |
| Pin 34 | CS — SPI chip select (serial config) |
| Pin 35 | SCLK — SPI serial clock |
| Pin 36 | SDIO — SPI serial data input/output |
| Pin 37 | SDO — SPI serial data output |
| Pin 38 | MODE — Output mode select (CMOS / LVDS DDR) |
| Pin 39 | FSR — Full-scale range select |
| Pin 40 | GND — Ground |
| Pin 41 | EP — Exposed thermal pad (connect to analog ground) |
Typical Applications
ADC1210S065HN/C1 is suitable for 7 applications: Communications IF/Baseband Digitization, Industrial Machine Vision, Portable Oscilloscope/Digitizer Channel, Ultrasound Receive-Channel Front End, Software-Defined Radio Receiver, Radar/EW Intermediate-Frequency Sampling, High-Speed Data Acquisition Card.
Communications IF/Baseband Digitization
The ADC1210S065HN/C1's 12-bit resolution and 65 MSPS sample rate make it a strong fit for intermediate-frequency (IF) and baseband digitization in software-defined radio (SDR) and small-cell base-station receivers. The 70 dBFS SNR at 65 MSPS with a 70 MHz IF input is sufficient for QAM demodulation with low EVM, while the selectable LVDS DDR output simplifies FPGA capture on multi-channel platforms. Designers typically place a 4:1 impedance-ratio balun between the mixer IF output and the ADC IN+/IN- pins, AC-coupling with 10 nF capacitors, and bias the input common-mode to VCM via 1 kohm resistors. Compared to a discrete SHA + flash-ADC chain, the integrated pipelined core reduces PCB area by roughly 60%.
Recommended
Industrial Machine Vision
The ADC1210S065HN/C1 digitizes high-speed line-scan or area-scan camera analog outputs in industrial machine-vision systems such as PCB inspection, food sorting, and surface-defect detection. The 12-bit depth captures the wide dynamic range required when both bright specular highlights and shadow regions appear in the same frame, while the 65 MSPS throughput supports 8K pixel line-scan rates up to 8 kHz. The exposed thermal pad of the HVQFN-40 package enables sustained operation in factory-floor ambient temperatures up to 85 C. A typical signal chain uses a transimpedance amplifier or differential driver feeding the ADC, with the LVDS DDR outputs routed directly into a Xilinx Spartan-7 or Xilinx Artix-7 FPGA for pixel processing.
Recommended
Portable Oscilloscope/Digitizer Channel
The ADC1210S065HN/C1 suits the analog front-end of a portable, battery-powered oscilloscope or data-acquisition module digitizing in the 25-30 MHz bandwidth class. At 65 MSPS, the ADC oversamples a 25 MHz analog front-end by more than 2x, enabling simple FIR filtering inside the FPGA for ENOB extension up to 13 effective bits. The 1.8 V analog supply combined with a power-down pin allows the ADC1210S065HN/C1 to draw < 5 mW in standby, which is essential for battery-powered field instruments targeting 8-12 hours of runtime. The 40-pin HVQFN (6x6) keeps the channel-area footprint below 36 mm^2, allowing 4-channel blocks to fit in a 100 x 60 mm enclosure.
Recommended
Ultrasound Receive-Channel Front End
The ADC1210S065HN/C1 is well-matched to the 12-bit, 40-65 MSPS segment of medical ultrasound receive-channel electronics where each transducer element is digitized with high dynamic range for harmonic imaging. The 12-bit resolution combined with the low-noise input network gives approximately 68 dBFS SNR, which is sufficient for second-harmonic imaging at 5-10 MHz. The exposed thermal pad of the HVQFN-40 package sustains continuous sampling in a 32- or 64-channel probe-head assembly. The selectable LVDS DDR output minimizes pin count on the probe cable, allowing 64 channels to route through a compact 0.5 mm-pitch FFC connector to the back-end FPGA beamformer.
Recommended
Software-Defined Radio Receiver
The ADC1210S065HN/C1 digitizes the second IF of a wideband SDR receiver covering HF to L-band amateur and commercial bands. At 65 MSPS, the ADC provides 32.5 MHz of Nyquist bandwidth, which after bandpass decimation in the FPGA yields the 30 dB SNR required for weak-signal digital modes such as FT8 and PSK31. The LVDS DDR interface minimizes signal-integrity challenges when routing the digital outputs to a Xilinx Kintex-7 or Spartan-7 FPGA over a 50 mm board distance. A 4:1 IF transformer (e.g. Mini-Circuits ADT4-1WT) drives the differential IN+/IN- inputs, while a 25 ppm TCXO drives the CLK+/CLK- differential input for frequency-stable sampling.
Recommended
Radar/EW Intermediate-Frequency Sampling
The ADC1210S065HN/C1's 12-bit resolution at 65 MSPS is adequate for digitizing the IF output of a short-range radar or electronic-warfare receiver in the L/S band, where pulse-compression processing in the FPGA can recover range and Doppler. The integrated differential input supports direct coupling to a single-ended SAW filter output via a 1:1 balun, eliminating an external op-amp stage. The LVDS DDR mode provides low-EMI digital outputs that are critical for sensitive RF sections housed in the same chassis. A typical reference design uses the ADC1210S065HN/C1 followed by a Xilinx Artix-7 FPGA running 2D FFT and constant-false-alarm-rate (CFAR) detection.
Recommended
High-Speed Data Acquisition Card
The ADC1210S065HN/C1 fits the analog-to-digital stage of a multi-channel PCI Express or PXI data acquisition card targeting 25 MHz analog bandwidth per channel. With 12 bits at 65 MSPS, each channel delivers 780 MB/s raw data rate, which a Xilinx Kintex-7 FPGA buffers into DDR3 memory before PCI Express 2.0 x8 uplink to the host. The exposed thermal pad of the HVQFN-40 package sustains continuous sampling across all 8-16 channels of the card. The LVDS DDR output mode keeps digital pin count manageable on dense multi-channel cards, where 16 parallel CMOS outputs per ADC would otherwise require a 2-layer BGA-to-FPGA trace routing scheme.
Recommended
Recommended Products Summary
Engineering reference data for ADC1210S065HN/C1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC1210S080HN/C1:5 | ADC1210S105HN/C1:5 | ADC1210S125HN/C1:5 | ADC1015S125HN/C1:5 | ADC1010S080HN/C1:5 | ADC1012D080HN/C1:5 | ADC1112D125HN-C18 |
|---|---|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | HVQFN-40 (6x6 mm) - same | HVQFN-40 (6x6 mm) - same | HVQFN-40 (6x6 mm) - same | HVQFN-40 (6x6 mm) - same | HVQFN-40 (6x6 mm) - same | HVQFN-40 (6x6 mm) - same | HVQFN-40 (6x6 mm) - same | HVQFN-40 (6x6 mm) - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 10 bit | 10 bit | 10/12 bit selectable | 11 bit |
| Sample Rate | 65 MSPS | 80 MSPS | 105 MSPS | 125 MSPS | 125 MSPS | 80 MSPS | 80 MSPS | 125 MSPS |
| Channels | 1 | 1 | 1 | 1 | 1 | 1 | 2 | 2 |
| Digital Output | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR |
| Analog Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Operating Temperature | -40 C to +85 C (industrial) | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C (AEC-Q100 grade) |
| Approx. Unit Price (1k qty) | $8.40 | $9.20 | $10.50 | $11.80 | $9.50 | $7.60 | $12.40 | $14.00 |
Key Differentiators
- Selectable CMOS or LVDS DDR digital output (vs ADC1010S080HN/C1:5)
- Pin-compatible speed-grade migration within ADC1210S family (vs ADS62P23IRGC25)
- Lower power consumption at 65 MSPS than higher-speed cousins (vs ADC1210S125HN/C1:5)
Design Notes
Place input capacitors and termination resistors within 3 mm of the IN+/IN- pins to minimize parasitic inductance and preserve SNR. Use a continuous analog ground pour stitched with ground vias on a 2 mm pitch around the HVQFN-40 package perimeter. The exposed pad (EP, pin 41) must be soldered to a 4 x 4 via array (0.3 mm drill, 1.0 mm pitch) connected to the analog ground plane. Keep the digital LVDS/CMOS output traces on a separate inner layer with no via stubs to avoid reflections; if vias are required, use 8-mil drill back-drilled vias.
Decouple the VA (analog 1.8 V) supply with a 10 uF X7R ceramic + 0.1 uF X7R + 10 nF C0G combination in parallel, with the smallest capacitor closest to the pin. Use a low-noise LDO such as the LT3042 or ADP1741 rather than a switching regulator to power the VA rail, because switching noise couples into the input network and degrades SNR. The VDR (digital output) supply can share a 1.8 V or 3.3 V rail, but place a ferrite bead between VDR and VA to prevent digital switching noise from corrupting the analog supply via the internal substrate connection.
Match the length of the LVDS DDR data outputs (D0-D11) and the DOR/CLK pairs to within 5 mil (0.13 mm) of each other to keep timing skew within the FPGA capture window. Use 100 ohm differential impedance routing with coupled microstrips on an inner stripline layer for best EMI/EMC performance. For the differential clock input, drive CLK+ and CLK- with a low-jitter LVPECL or LVDS source such as a Si5351 or LMX2485; clock jitter above 1 ps RMS directly degrades SNR by 1 dB per 2x of jitter at 65 MSPS.
Do not apply the analog input signal before the VA supply has stabilized - the ESD protection diodes can be forward-biased and damage the input stage. Tie the MODE pin (pin 38) to VDR for LVDS DDR mode or to ground for CMOS mode; leaving it floating causes undefined output behavior. Avoid driving the IN+/IN- inputs with a single-ended signal below -0.3 V or above VA+0.3 V - the internal ESD diodes clamp and inject distortion. When using the internal reference, add a 0.1 uF + 10 uF capacitor between the FSRA pin and ground to filter reference noise; external reference is recommended only if multiple ADCs must track within 0.5 LSB.
Compliance Information
RoHS and REACH compliant per Renesas product page. Industrial temperature grade -40 C to +85 C; not AEC-Q100 qualified. Choose ADC1112D125HN-C18 for automotive-grade equivalent.
