ADC1413S080HN-C18 - 14-bit 80MSPS Single-Channel ADC | Renesas
MPN: ADC1413S080HN-C18 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $32.5 | $32.50 |
| 10 | $29.2 | $292.00 |
| 100 | $25.8 | $2,580.00 |
| 500 | $22.4 | $11,200.00 |
| 1,000 | $19.95 | $19,950.00 |
ADC1413S080HN-C18 Overview
An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that samples continuous analog input voltages and converts them into discrete digital codes for processing by DSPs, FPGAs, or microcontrollers. Within the broader semiconductor hierarchy, the ADC1413S080HN-C18 belongs to the data-converter family, which sits under the signal-chain taxonomy alongside DACs, amplifiers, and comparators. Pipeline ADCs specifically use a cascade of low-resolution stages to achieve high sample rates with high resolution, making them the default architecture for communications, instrumentation, and radar receivers operating between 10 MSPS and 250 MSPS.
Key features include 14-bit resolution, 80 MSPS maximum sample rate, an SNR of approximately 73 dBFS (typical input), an SFDR of better than 85 dBFS, and a single 1.8 V analog supply. The device exposes differential analog inputs (VINP/VINN), an internal reference, and a JESD204A subclass-0 link that requires only four serial lanes at typical link rates around 1.6 Gbps. The HVQFN-32 (5x5 mm) package offers low thermal resistance through the exposed pad.
Architecturally, the ADC1413S080HN-C18 combines a switched-capacitor pipeline front end with a digital error-correction backend and an integrated PLL-less JESD204A transmitter. Latency is fixed at a small multiple of the conversion clock, simplifying deterministic system timing in multi-channel synchronous acquisition systems. Programmable gain and offset trim are accessible through the SPI configuration port, allowing per-channel calibration in production.
Typical applications include broadband communications receivers, IF-sampling software-defined radio (SDR), medical imaging front ends, and high-speed industrial test and measurement digitizers. The combination of 14-bit linearity, 80 MSPS throughput, and JESD204A serial output makes the part especially well suited to multi-board synchronization where lane count must be kept manageable.
When designing with this ADC, use a balanced-differential analog front end with a wideband ADC driver such as the LMH6554 or ADA4927 to preserve SFDR, and route the JESD204A lanes with controlled 100-ohm differential impedance and length matching to within a few millimeters. The exposed pad must be soldered to a continuous ground plane to meet the datasheet thermal and electrical performance figures.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found on the Renesas product page alone, including same-family variants and pin-compatible JESD204A ADCs from competing vendors for engineers evaluating cross-vendor sourcing strategies.
Drop-in alternatives for ADC1413S080HN-C18 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC1413S080HN-C18 (same form factor and footprint) — differing in Package, Resolution, Number of Channels, Input Type, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC1413S080HN-C1
✅ Drop-In📋 Reference alternative (not in catalog)
ADC1213S080HN-C18
✅ Drop-In✓ In Stock
$9.45 / Unit
View Datasheet →ADC1413S105HN-C18
✅ Drop-In📋 Reference alternative (not in catalog)
ADC1413D080HN-C18
✅ Drop-In✓ In Stock
$32.1 / Unit
View Datasheet →ADC1213S125HN-C1
✅ Drop-In✓ In Stock
$18.45 / Unit
View Datasheet →ADS62P23IRGC25
✅ Drop-In✓ In Stock
$18.85 / Unit
View Datasheet →ADC1413S080HN-C18 Maximum Ratings & Electrical Characteristics
| Resolution | 14 bit |
| Number of Channels | 1 |
| Sample Rate (max) | 80 MSPS |
| Architecture | Pipelined |
| Input Type | Differential |
| Digital Interface | Serial JESD204A (subclass 0) |
| Analog Supply Voltage | 1.8 V |
| Digital Supply Voltage | 1.8 V |
| SNR (typical) | 73 dBFS |
| Package | 32-pin HVQFN Exposed Pad (5x5 mm) |
| Operating Temperature Range | -40C to +85C |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Internal Reference | Yes |
| SPI Configuration Port | Yes |
ADC1413S080HN-C18 Pin Configuration
| Pin 1 | AVDD — Analog 1.8 V supply |
| Pin 2 | VINP — Differential analog input (positive) |
| Pin 3 | VINN — Differential analog input (negative) |
| Pin 4 | VCM — Common-mode voltage output |
| Pin 5 | REFP — Internal reference decoupling (positive) |
| Pin 6 | REFN — Internal reference decoupling (negative) |
| Pin 7 | AGND — Analog ground |
| Pin 8 | CLKP — Differential clock input (positive) |
| Pin 9 | CLKN — Differential clock input (negative) |
| Pin 10 | DVDD — Digital 1.8 V supply |
| Pin 11 | DGND — Digital ground |
| Pin 12 | SCLK — SPI configuration clock |
| Pin 13 | SDIO — SPI configuration data I/O |
| Pin 14 | CSB — SPI configuration chip select (active low) |
| Pin 15 | RESETB — RESET (active low) |
| Pin 16 | PDN — Power-down (active high) |
| Pin 17 | TEST — Factory test pin (leave floating) |
| Pin 18 | NC — Not connected (per datasheet) |
| Pin 19 | SERDOUT0_P — JESD204A serial data lane 0 (positive) |
| Pin 20 | SERDOUT0_N — JESD204A serial data lane 0 (negative) |
| Pin 21 | SERDOUT1_P — JESD204A serial data lane 1 (positive) |
| Pin 22 | SERDOUT1_N — JESD204A serial data lane 1 (negative) |
| Pin 23 | SERDOUT2_P — JESD204A serial data lane 2 (positive) |
| Pin 24 | SERDOUT2_N — JESD204A serial data lane 2 (negative) |
| Pin 25 | SERDOUT3_P — JESD204A serial data lane 3 (positive) |
| Pin 26 | SERDOUT3_N — JESD204A serial data lane 3 (negative) |
| Pin 27 | SYSREF_P — JESD204A SYSREF (positive) |
| Pin 28 | SYSREF_N — JESD204A SYSREF (negative) |
| Pin 29 | AVDD — Analog 1.8 V supply (second tap) |
| Pin 30 | DVDD — Digital 1.8 V supply (second tap) |
| Pin 31 | AGND — Analog ground (second tap) |
| Pin 32 | DGND — Digital ground (second tap) |
Typical Applications
ADC1413S080HN-C18 is suitable for 6 applications: Broadband Communications Receiver IF Sampling, Software-Defined Radio (SDR) Front End, Medical Ultrasound Beamformer, High-Speed Industrial Test Instrumentation, Radar and Lidar Digitizer, Data Acquisition Card for Embedded Systems.
Broadband Communications Receiver IF Sampling
The ADC1413S080HN-C18 fits broadband communications receivers that digitize intermediate-frequency (IF) signals after the analog downconversion stage. Its 14-bit resolution delivers approximately 73 dBFS SNR, providing enough dynamic range to resolve small wanted signals in the presence of large blockers, while the 80 MSPS sample rate supports IF bandwidths of up to roughly 30 MHz under Nyquist sampling. The JESD204A subclass-0 serial output drastically reduces board-routing complexity compared to parallel LVDS ADCs, and its fixed pipeline latency simplifies deterministic system timing. The 32-HVQFN exposed-pad footprint is compact enough for multi-channel receiver cards that synchronize several ADCs to a common clock for diversity or MIMO systems.
Recommended
Software-Defined Radio (SDR) Front End
The ADC1413S080HN-C18 is well matched to SDR platforms that need a high dynamic range, JESD204A-output ADC behind the analog front end. The 14-bit linearity preserves modulation accuracy for narrowband waveforms, and the 80 MSPS rate is sufficient to digitize HF, VHF, and low-UHF bands directly. The JESD204A serial link streams samples into the host FPGA where digital downconversion and channelization run in logic, reducing analog complexity. The single 1.8 V supply simplifies power-tree design in portable SDR equipment, and the small 32-HVQFN footprint suits handheld form factors. Compared to a parallel LVDS ADC of equivalent performance, the ADC1413S080HN-C18 saves roughly 16 to 20 board-routing traces.
Recommended
Medical Ultrasound Beamformer
The ADC1413S080HN-C18 fits medical ultrasound beamformer front ends that digitize time-gain-compensated (TGC) RF signals from piezoelectric transducer arrays. The 80 MSPS sample rate is sufficient for 40 MHz ultrasound probes under Nyquist, and the 14-bit dynamic range quantizes the small return echoes that carry diagnostic information. JESD204A serial output minimizes the connector pin count between the probe head and the back-end processing FPGA, which is valuable where space is constrained. Synchronous multi-channel acquisition is straightforward because the JESD204A link supports deterministic latency via SYSREF. The exposed thermal pad keeps junction temperature low when many channels operate concurrently in a single chassis.
Recommended
High-Speed Industrial Test Instrumentation
The ADC1413S080HN-C18 suits high-speed industrial test instrumentation including oscilloscope front ends, spectrum analyzer IF digitizers, and automated test equipment (ATE) capture cards. The 80 MSPS rate handles real-time sampling of signals up to approximately 30 MHz without undersampling artifacts, and 14-bit resolution preserves measurement accuracy for production-line quality screening. JESD204A serial output streams samples to the host processor over a deterministic link, allowing deep acquisition memory to be located remotely. The single 1.8 V supply eases thermal design in densely populated ATE racks, and the small 32-HVQFN package enables compact channel-density per square inch of PCB area.
Recommended
Radar and Lidar Digitizer
The ADC1413S080HN-C18 supports radar and lidar receiver digitizer boards that need high dynamic range at moderate bandwidths. With 14-bit resolution and 80 MSPS, the part digitizes baseband or low-IF outputs of FMCW radar front ends and pulsed lidar detectors while preserving the small returns that matter for object detection. The JESD204A subclass-0 interface supports deterministic multi-channel synchronization, a critical requirement for phased-array radar. Compared to parallel-output ADCs of equivalent performance, the JESD204A link cuts PCB trace count by an order of magnitude and simplifies timing closure. The exposed-pad package keeps thermal performance predictable even in enclosed IP67 sensor housings.
Recommended
Data Acquisition Card for Embedded Systems
The ADC1413S080HN-C18 fits data acquisition cards embedded in industrial controllers, machine-vision systems, and scientific instruments. With 14-bit resolution at 80 MSPS, the part captures transient analog events such as motor back-EMF, vibration signatures, and high-speed sensor outputs. The serial JESD204A output streams samples into an FPGA or SoC where the data is filtered, decimated, and forwarded to the host processor. The 32-HVQFN exposed-pad package occupies minimal board area, leaving more room for analog front-end conditioning, isolation barriers, and connector placement. Operating from a single 1.8 V supply simplifies the local LDO tree and improves overall power efficiency of the acquisition card.
Recommended
Recommended Products Summary
Engineering reference data for ADC1413S080HN-C18 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC1413S080HN-C1 | ADC1213S080HN-C18 | ADC1413S105HN-C18 | ADC1413D080HN-C18 | ADC1213S125HN-C1 | ADS62P23IRGC25 |
|---|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Texas Instruments |
| Package | 32-pin HVQFN Exposed Pad (5x5 mm) | 32-pin HVQFN Exposed Pad - same | 32-pin HVQFN Exposed Pad - same | 32-pin HVQFN Exposed Pad - same | 32-pin HVQFN Exposed Pad - same | 32-pin HVQFN Exposed Pad - same | VQFN-64 - DIFFERENT |
| Resolution | 14 bit | 14 bit | 12 bit | 14 bit | 14 bit | 12 bit | 12 bit |
| Sample Rate (max) | 80 MSPS | 80 MSPS | 80 MSPS | 105 MSPS | 80 MSPS | 125 MSPS | 80 MSPS |
| Number of Channels | 1 | 1 | 1 | 1 | 2 | 1 | 2 |
| Digital Interface | JESD204A (subclass 0) | JESD204A (subclass 0) | JESD204A (subclass 0) | JESD204A (subclass 0) | JESD204A (subclass 0) | JESD204A (subclass 0) | Parallel LVDS - DIFFERENT |
| Analog Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 3.3 V - DIFFERENT |
| Pin-to-Pin Compatible | Yes | Yes | Yes | Yes | Yes | Yes | No (64-VQFN vs 32-HVQFN) |
Key Differentiators
- JESD204A subclass-0 serial output minimizes board pin count (vs ADS62P23IRGC25 (TI))
- 14-bit resolution at 80 MSPS in compact 32-HVQFN (vs ADC1213S080HN-C18 (Renesas 12-bit))
- Pin-compatible with 12-bit and 105 MSPS Renesas family (vs ADC1413S105HN-C18 (Renesas 105 MSPS))
Design Notes
Route the four JESD204A serial lanes as 100-ohm differential pairs with intra-pair length matching below 0.13 mm (5 mil) and inter-pair matching below 6.4 mm (250 mil). Use a continuous ground plane beneath the lanes and avoid splitting the reference plane across the serial output region. The exposed thermal pad of the 32-HVQFN package must be soldered to a continuous ground pour with at least 8 thermal vias (0.3 mm drill, 0.6 mm pitch) to meet datasheet thermal resistance figures.
Power the AVDD and DVDD rails from separate low-noise LDOs such as the LT3042 or ADP1741 rather than chaining off a common switching regulator. Place 1 uF X7R ceramic decoupling capacitors within 2 mm of each AVDD/DVDD pin, supplemented by a 10 uF bulk capacitor near the supply pins. Estimated: based on typical AVDD/DVDD pin count of 4, a fully populated board may draw approximately 70 to 100 mA total supply current at 80 MSPS, requiring an LDO with at least 200 mA headroom for transient response.
Drive the differential analog inputs VINP/VINN through a wideband low-distortion ADC driver such as the LMH6554, ADA4927, or THS4509. Maintain proper input common-mode voltage using the on-chip VCM output, and add external common-mode chokes if the source impedance is greater than 50 ohms per side. For best SFDR, terminate the analog inputs with 50-ohm resistors close to the ADC pins and avoid running analog traces parallel to the JESD204A serial lanes.
Do not float the TEST pin - tie it to DGND through a 10 kohm resistor to avoid inadvertent factory-test behavior at power-on. Apply the RESETB pulse after both AVDD and DVDD rails have stabilized, and verify that the JESD204A link establishes a stable SYNC~ (deasserted) before starting data acquisition. The PDN pin must be held low during normal operation; leaving it floating can cause intermittent shutdown that is difficult to debug on the bench.
Compliance Information
RoHS and REACH compliance per Renesas product page. AEC-Q100 not applicable for commercial-grade ADC; consult Renesas automotive-grade variants if required for automotive applications.
