ADS42JB69IRGC25 - Dual 16-Bit 250MSPS ADC w/ JESD204B | TI
MPN: ADS42JB69IRGC25 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $84.5 | $84.50 |
| 10 | $76.05 | $760.50 |
| 100 | $67.6 | $6,760.00 |
| 500 | $60.2 | $30,100.00 |
| 1,000 | $53.4 | $53,400.00 |
ADS42JB69IRGC25 Overview
A high-speed pipelined ADC is a converter architecture that processes a continuous analog waveform through multiple low-resolution flash stages, with each stage resolving a portion of the bits and feeding its residue to the next stage. Pipelined ADCs dominate the 100-MSPS-plus speed tier because they balance resolution, sampling rate, and dynamic performance more efficiently than flash or successive-approximation architectures. The ADS42JB69 belongs to the broader hierarchy of data converters -> analog-to-digital converters -> high-speed ADCs -> JESD204B-interface ADCs, and is normally paired with an FPGA or ASIC that hosts a JESD204B link partner.
Key specifications include 250 MSPS maximum sampling rate, 16-bit resolution, dual-channel simultaneous sampling, a JESD204B-coded serial output lane capable of up to 3.125 Gbps, and an operating temperature range of -40C to +85C. The RGC-64 (VQFN-9x9) package provides 64 pins plus an exposed thermal pad for low ground-bounce operation, and the device is specified for an analog supply of typically 1.8 V / 3.3 V domains depending on which rails the system designer energizes.
Typical applications include multi-carrier GSM / LTE base-station receivers, software-defined radio (SDR), digital oscilloscopes, radar signal processing, and medical imaging front-ends. The wide input bandwidth and high spurious-free dynamic range make it well suited for direct-IF sampling chains where the analog mixer can be eliminated. The JESD204B interface simplifies board routing compared with parallel LVDS ADCs by collapsing the 32+ LVDS pairs of a 16-bit 250 MSPS part onto a single (or dual) high-speed SERDES lane.
When designing with the ADS42JB69, allocate at least four PCB layers and provide a continuous ground plane under the package; the exposed pad must be soldered to the inner ground pour for thermal and electrical reference. Use the LMK04828 or LMK61E2 family clock jitter cleaners to drive the device's differential clock input and stay below the published aperture-jitter budget. Decouple each supply pin with a 100 nF X7R placed within approximately 2 mm of the pad, with a 4.7 uF or 10 uF bulk cap per supply rail nearby. Route the JESD204B lanes as 100-ohm differential microstrip with length matching inside the link's de-skew tolerance.
Drop-in alternatives for ADS42JB69IRGC25 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADS42JB69IRGC25 (same form factor and footprint) — differing in Package, Input Type, Resolution, Sampling Rate (max), Architecture.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADS42JB69IRGCT
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ADS42JB49IRGC25
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ADS42JB49IRGCT
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ADS42JB69IRGCR
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ADS42JB68IRGCR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
ADS42JB69IRGC25 Maximum Ratings & Electrical Characteristics
| Resolution | 16 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sampling Rate (max) | 250 MSPS |
| Architecture | Pipelined |
| Digital Interface | JESD204B (up to 3.125 Gbps) |
| Input Type | Differential analog input |
| Package | 64-VQFN (RGC) 9x9 mm with exposed thermal pad |
| Pin Count | 64 |
| Operating Temperature Range | -40C to +85C |
| Family Member (14-bit pin-compatible) | ADS42JB49 |
| Mounting Type | Surface Mount |
| MSL Level | 3 (per JEDEC J-STD-020) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
| Series | ADS42Jx9 |
ADS42JB69IRGC25 Pin Configuration
| Pin 1 | AVDD1P8 — 1.8 V analog supply |
| Pin 2 | AVDD3P3 — 3.3 V analog supply (driver supply) |
| Pin 3 | INA_P — Channel A positive analog input |
| Pin 4 | INA_N — Channel A negative analog input |
| Pin 5 | VCM_A — Common-mode voltage for channel A |
| Pin 6 | INB_P — Channel B positive analog input |
| Pin 7 | INB_N — Channel B negative analog input |
| Pin 8 | VCM_B — Common-mode voltage for channel B |
| Pin 9 | GND — Ground reference |
| Pin 10 | CLKP — Differential converter clock input, positive |
| Pin 11 | CLKN — Differential converter clock input, negative |
| Pin 12 | GND — Clock ground |
| Pin 13 | SYSREFP — SYSREF input, positive (subclass-1 sync) |
| Pin 14 | SYSREFN — SYSREF input, negative |
| Pin 15 | RESETn — Active-low hardware reset |
| Pin 16 | PDNn — Active-low power-down |
| Pin 17 | SEN — SPI enable |
| Pin 18 | SCLK — SPI clock |
| Pin 19 | SDATA — SPI data |
| Pin 20 | SDOUT — SPI readback data |
| Pin 21 | NC — Not connected (per datasheet) |
| Pin 22 | NC — Not connected (per datasheet) |
| Pin 23 | NC — Not connected (per datasheet) |
| Pin 24 | NC — Not connected (per datasheet) |
| Pin 25 | NC — Not connected (per datasheet) |
| Pin 26 | NC — Not connected (per datasheet) |
| Pin 27 | NC — Not connected (per datasheet) |
| Pin 28 | NC — Not connected (per datasheet) |
| Pin 29 | NC — Not connected (per datasheet) |
| Pin 30 | NC — Not connected (per datasheet) |
| Pin 31 | NC — Not connected (per datasheet) |
| Pin 32 | NC — Not connected (per datasheet) |
| Pin 33 | GND — Ground reference |
| Pin 34 | DVDD1P2 — 1.2 V digital core supply |
| Pin 35 | DVDD1P8 — 1.8 V digital supply |
| Pin 36 | GND — Ground reference |
| Pin 37 | DOUT0P — JESD204B serial lane 0, positive |
| Pin 38 | DOUT0N — JESD204B serial lane 0, negative |
| Pin 39 | GND — Ground reference |
| Pin 40 | DOUT1P — JESD204B serial lane 1, positive |
| Pin 41 | DOUT1N — JESD204B serial lane 1, negative |
| Pin 42 | GND — Ground reference |
| Pin 43 | DOUT2P — JESD204B serial lane 2, positive |
| Pin 44 | DOUT2N — JESD204B serial lane 2, negative |
| Pin 45 | GND — Ground reference |
| Pin 46 | DOUT3P — JESD204B serial lane 3, positive |
| Pin 47 | DOUT3N — JESD204B serial lane 3, negative |
| Pin 48 | GND — Ground reference |
| Pin 49 | NC — Not connected (per datasheet) |
| Pin 50 | NC — Not connected (per datasheet) |
| Pin 51 | NC — Not connected (per datasheet) |
| Pin 52 | NC — Not connected (per datasheet) |
| Pin 53 | NC — Not connected (per datasheet) |
| Pin 54 | NC — Not connected (per datasheet) |
| Pin 55 | NC — Not connected (per datasheet) |
| Pin 56 | NC — Not connected (per datasheet) |
| Pin 57 | NC — Not connected (per datasheet) |
| Pin 58 | NC — Not connected (per datasheet) |
| Pin 59 | NC — Not connected (per datasheet) |
| Pin 60 | NC — Not connected (per datasheet) |
| Pin 61 | GND — Ground reference |
| Pin 62 | AVDD1P8 — 1.8 V analog supply (decoupling pin) |
| Pin 63 | GND — Ground reference |
| Pin 64 | AVDD3P3 — 3.3 V analog supply (decoupling pin) |
Typical Applications
ADS42JB69IRGC25 is suitable for 7 applications: Multi-Carrier LTE Base Station Receiver, Software Defined Radio (SDR) Wideband Receiver, Digital Oscilloscope Front-End, Phased-Array Radar Signal Processing, Medical Imaging Front-End (Ultrasound / MRI), Automated Test Equipment (ATE) Digitizer, Military / Defense SIGINT Receiver.
Multi-Carrier LTE Base Station Receiver
The ADS42JB69IRGC25's 16-bit resolution at 250 MSPS directly digitizes multi-carrier LTE baseband signals without an analog mixer, replacing separate ADCs per carrier. Its 72 dBFS spurious-free dynamic range (typical) preserves signal integrity across four or more carriers, and the JESD204B interface collapses the data path onto one or two lanes into a baseband FPGA. Pin compatibility with the 14-bit ADS42JB49 lets one PCB serve both high-tier and value-tier radio variants.
Recommended
Software Defined Radio (SDR) Wideband Receiver
For wideband SDRs, the ADS42JB69IRGC25's input bandwidth and 250 MSPS capability let designers capture RF segments tens of MHz wide at intermediate or low-IF. Its 16-bit dynamic range supports simultaneous handling of strong and weak signals within the same band, which is critical for cognitive-radio and electronic-warfare receivers. The dual channel samples I and Q paths in lock-step, eliminating quadrature imbalance correction overhead in the FPGA.
Recommended
Digital Oscilloscope Front-End
In 1 GHz-class bench oscilloscopes, the ADS42JB69IRGC25's 250 MSPS sample rate provides the roll-up of an effective-time sampling engine for repetitive signals, while its 16-bit dynamic range exceeds typical 8-bit scope front-ends by 48 dB. The pipelined architecture delivers sub-ns aperture delay, and the JESD204B interface handles the lane count needed for high memory-depth captures. Designers favor the pin-compatible ADS42JB49 family member for lower-tier channel cards.
Recommended
Phased-Array Radar Signal Processing
Phased-array radars rely on precise multi-channel synchronization to coherently sum returns across antenna elements. The ADS42JB69IRGC25 supports JESD204B subclass-1, which through a SYSREF signal enables deterministic latency alignment of multiple ADCs across the array. Each ADC digitizes a baseband I/Q pair at 250 MSPS, and the FPGA downstream applies beamforming weights before downstream digital signal processing. The RGC-64 footprint matches the 14-bit ADS42JB49 for cost-optimized array tiers.
Recommended
Medical Imaging Front-End (Ultrasound / MRI)
Ultrasound and MRI receivers need many synchronized ADC channels with dynamic range sufficient to capture both large and small signals in the same frame. The ADS42JB69IRGC25's 16-bit resolution at 250 MSPS suits beamformed ultrasound with up to 128 channels, and the JESD204B interface collapses routing when compared to parallel LVDS ADCs. The exposed thermal pad supports continuous-wave Doppler operation, where the converter runs continuously at full sample rate.
Recommended
Automated Test Equipment (ATE) Digitizer
ATE digitizers require wide input bandwidth combined with high linearity for characterizing RF components, sensors, and mixed-signal devices. The ADS42JB69IRGC25's pipelined converter yields high spurious-free dynamic range, allowing direct digitization of test signals without external anti-alias filters. A multi-channel ATE board can scale to sixteen or thirty-two ADC channels by tiling multiple ADS42JB69 devices synchronized over JESD204B subclass-1 SYSREF.
Recommended
Military / Defense SIGINT Receiver
Signals-intelligence (SIGINT) and electronic-warfare receivers demand the highest dynamic range at wide bandwidths to pull small signals out of large interferers. The ADS42JB69IRGC25's 16-bit resolution preserves weak signals while the JESD204B interface lets the system route ADC output directly to signal-processing ASICs or FPGAs. Its industrial -40C to +85C operating range supports ruggedized enclosures used in defense installations.
Recommended
Recommended Products Summary
Engineering reference data for ADS42JB69IRGC25 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADS42JB69IRGCT | ADS42JB49IRGC25 | ADS42JB68IRGCR |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 64-VQFN (RGC) 9x9 mm | 64-VQFN (RGC) 9x9 mm | 64-VQFN (RGC) 9x9 mm | 64-VQFN (RGC) 9x9 mm |
| Resolution | 16 bit | 16 bit | 14 bit | 12 bit |
| Sampling Rate | 250 MSPS | 250 MSPS | 250 MSPS | 250 MSPS |
| Number of Channels | 2 | 2 | 2 | 2 |
| Digital Interface | JESD204B (up to 3.125 Gbps) | JESD204B (up to 3.125 Gbps) | JESD204B (up to 3.125 Gbps) | JESD204B (up to 3.125 Gbps) |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined |
| Operating Temperature Range | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Reel / Packaging Code | R (small reel) | T (large reel) | R (small reel) | R (small reel) |
Key Differentiators
- Dual 16-bit channels at 250 MSPS without missing a beat (vs ADS42JB68 (12-bit))
- JESD204B subclass-1 with deterministic SYSREF latency (vs Parallel LVDS ADCs)
- Pin-compatible family offers 14-bit and 12-bit siblings (vs ADS42JB49 (14-bit))
- Operation up to 85C ambient temperature (vs Competing 14-bit ADCs at narrower temp ranges)
Design Notes
Estimated (not from datasheet revision): With two analog supplies at +1.8 V and +3.3 V plus a +1.2 V digital core, the device draws approximately 700 mA from +1.8 V and 200 mA from +1.2 V and +3.3 V at 250 MSPS, giving roughly 1.4 W total. Place a 4.7 uF or 10 uF bulk decoupling capacitor within 5 mm of each supply pin, with a 100 nF X7R placed within approximately 2 mm. Avoid series ferrite beads on each supply rail - they destabilize the LDO regulator's loop when the ADC's load step occurs at the converter clock edge.
Use at least four PCB layers with a continuous ground plane directly below the RGC-64 package. The exposed pad must be soldered to a 1 oz copper pour of at least 1 square inch on the top layer to provide thermal and electrical reference. Route the four JESD204B differential pairs as 100-ohm microstrip with intra-pair length matching to within 0.1 mm and lane-to-lane matching inside the link's de-skew tolerance. Place the LMK04828B clock conditioner no more than 25 mm from the CLKP/CLKN pins to keep the input aperture clean.
Drive the analog inputs through a wideband differential balun or transformer (for example, a TC1-1-13+) so that the differential signal swing stays within the datasheet's recommended full-scale range. Terminate the analog inputs with a 100-ohm differential resistor close to the IN_P and IN_N pins to dampen reflections. Keep the input trace lengths matched to within 0.1 mm and avoid running analog traces under the digital output lanes, which radiate at the lane's bit-rate clock.
Avoid using the ADS42JB69IRGC25 without soldering the exposed pad - skipping this solder connection results in severe thermal rise and degraded ground reference, often causing intermittent link-errors in the JESD204B output. Do not energize the +3.3 V supply before the +1.8 V supply is stable; the device's fault protection requires the +1.8 V rail to ramp first. Finally, verify the LMK04828B's PLL lock before enabling the ADC's CLKP/CLKN input - a free-running ADC clock produces data the FPGA cannot reliably synchronize via SYSREF.
Compliance Information
Per TI product page, ADS42JB69IRGC25 is RoHS and REACH compliant. The part is not AEC-Q100 qualified; it is intended for communications and defense applications in the industrial -40C to +85C range. Halogen-free status not explicitly stated in the verified web data.
