ADS5484IRGC25 - 16-Bit 170MSPS ADC LVDS 64-VQFN | TI
MPN: ADS5484IRGC25 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $78.5 | $78.50 |
| 10 | $71.2 | $712.00 |
| 100 | $64.85 | $6,485.00 |
| 500 | $58.4 | $29,200.00 |
| 1,000 | $52.1 | $52,100.00 |
ADS5484IRGC25 Overview
A pipelined ADC is a high-speed successive-approximation architecture that resolves an analog input by passing it through a cascade of low-resolution flash stages, each clocked by one ADC period. Within the broader signal chain, an ADC like the ADS5484 sits between the analog front end (amplifiers, filters, anti-alias stages) and the digital domain (FPGA, ASIC, DSP), where it converts conditioned real-world signals into discrete digital codes for processing.
Key features of the ADS5484IRGC25 include buffered analog inputs for high source-impedance isolation, low spurious-free dynamic range (SFDR) and high signal-to-noise ratio (SNR) optimized for wideband input frequencies, an internal reference, and a flexible LVDS output bus. It is specified over the industrial temperature range of -40C to +85C, built on TI's complementary bipolar BiCom3 process, and integrates a 64-VQFN PowerPAD that exposes the die paddle for low thermal resistance.
Typical applications include communications receivers, test and measurement instrumentation, medical imaging front ends, radar and LiDAR signal chains, and high-speed data acquisition. The ADS5484 is pin-compatible with the ADS5485 (200 MSPS), ADS5483 (135 MSPS), ADS5482 (105 MSPS), and ADS5481 (80 MSPS), enabling a single PCB layout to support a portfolio of speed grades.
For design, place input and reference bypass capacitors as close to the IC as the layout allows, and stitch the exposed pad with multiple thermal vias to a solid ground plane. The ADS5484 is drop-in compatible within the ADS548x family - the ADS5484IRGC25, ADS5485IRGC25, ADS5483IRGCTG4 and ADS5482IRGC25 share the same 64-VQFN PowerPAD footprint.
This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes that go beyond what the manufacturer datasheet alone provides.
Drop-in alternatives for ADS5484IRGC25 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADS5484IRGC25 (same form factor and footprint) — differing in Input Type, Resolution, Package, Number of Channels, Sample Rate.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADS5485IRGC25
✅ Drop-In✓ In Stock
$52.18 / Unit
View Datasheet →ADS5483IRGCTG4
✅ Drop-In📋 Reference alternative (not in catalog)
ADS5482IRGC25
✅ Drop-In📋 Reference alternative (not in catalog)
ADS5481IRGC25
✅ Drop-In✓ In Stock
$49.85 / Unit
View Datasheet →ADS5484IRGCR
✅ Drop-In📋 Reference alternative (not in catalog)
ADS5484IRGCT
✅ Drop-In📋 Reference alternative (not in catalog)
ADS5484IRGC25 Maximum Ratings & Electrical Characteristics
| Resolution | 16 bit |
| Sample Rate | 170 MSPS |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Input Type | Buffered differential |
| Analog Supply Voltage | 5 V |
| Digital Supply Voltage | 3.3 V |
| Digital Output Interface | LVDS-compatible |
| Reference Type | Internal |
| Operating Temperature Range | -40C to +85C |
| Package | 64-VQFN PowerPAD (9x9 mm) |
| Mounting Type | Surface Mount |
| Process Technology | BiCom3 complementary bipolar |
| RoHS Status | Compliant |
| Pin-to-Pin Family | ADS5481/82/83/84/85 compatible |
ADS5484IRGC25 Pin Configuration
| Pin 1 | AVDD — Analog 5V supply |
| Pin 10 | VINP — Analog input positive (differential) |
| Pin 11 | VINN — Analog input negative (differential) |
| Pin 20 | REFT — Internal reference top |
| Pin 21 | REFB — Internal reference bottom |
| Pin 30 | DRVDD — Digital 3.3V supply |
| Pin 40 | CLK — Sample clock input |
| Pin 50 | OUT0P — LVDS output bit 0 positive |
| Pin 51 | OUT0N — LVDS output bit 0 negative |
| Pin 64 | DRGND — Digital ground |
Typical Applications
ADS5484IRGC25 is suitable for 6 applications: Communications Receiver IF Digitization, Test and Measurement Instrumentation, Medical Imaging Front End (Ultrasound / MRI), Radar and LiDAR Signal Acquisition, High-Speed Data Acquisition Systems, Spectrum Analyzer and RF Digitizer.
Communications Receiver IF Digitization
The ADS5484IRGC25's 170 MSPS sample rate and 16-bit resolution make it ideal for digitizing intermediate-frequency (IF) signals in software-defined radio and LTE/5G base station receivers. With 5V analog and 3.3V LVDS digital supplies, it directly feeds an FPGA baseband processor. The buffered inputs isolate the preceding SAW filter from switching kickback, preserving signal integrity in the IF strip. Per TI, the ADS548x family delivers high SFDR at high input frequencies, which is critical when capturing multi-carrier IF signals where spurious content can desensitize the receiver.
Recommended
Test and Measurement Instrumentation
Oscilloscopes, spectrum analyzers, and arbitrary waveform digitizers leverage the ADS5484IRGC25's 16-bit ENOB and 170 MSPS to capture wideband transient signals. The buffered differential input accommodates single-ended-to-differential front-end amplifier outputs (e.g., THS4631) and the LVDS output bus streams data into an FPGA or ASIC DSP. The 64-VQFN PowerPAD package simplifies thermal management in compact bench instruments where board density is high. Per the TI datasheet, this ADC maintains low noise and high SFDR across the full industrial temperature range.
Recommended
Medical Imaging Front End (Ultrasound / MRI)
Ultrasound beamformers and MRI receiver chains use the ADS5484IRGC25 to digitize low-level analog signals after the LNA and TGC stages. The buffered input reduces kickback into sensitive transducer preamps, while 16-bit resolution preserves dynamic range for tissue-contrast imaging. Its 170 MSPS rate comfortably covers the 50-80 MHz ultrasound IF band. Per TI, the BiCom3 bipolar process offers low noise at high IF frequencies, important when the imaging signal sits just above the noise floor of the receiver chain.
Recommended
Radar and LiDAR Signal Acquisition
Phased-array radar and LiDAR digitizer subsystems use the ADS5484IRGC25 to sample IF or baseband returns at 170 MSPS. The 16-bit dynamic range captures both strong and weak returns without saturating, while the LVDS output drives high-speed FPGAs (e.g., Kintex, Virtex) for FFT-based range processing. The 64-VQFN PowerPAD layout supports dense multi-channel arrays. Per TI's family datasheet, the ADS548x maintains ENOB at high input frequencies required by wideband chirp and pulsed radar signals.
Recommended
High-Speed Data Acquisition Systems
Multi-channel data-acquisition cards in industrial automation, vibration analysis, and rotating-machinery monitoring use the ADS5484IRGC25 for 16-bit, 170 MSPS capture. The buffered input accepts high-impedance piezoelectric or strain-gauge amplifier outputs, and the LVDS bus enables long PCB traces to the FPGA without signal degradation. The pin-compatible ADS548x family lets designers scale sampling rate per channel by swapping speed grades. Per TI, the industrial -40C to +85C temperature range supports factory-floor deployment.
Recommended
Spectrum Analyzer and RF Digitizer
Modern spectrum analyzers and RF digitizers use the ADS5484IRGC25 at the back end of the IF strip. With 16-bit resolution and 170 MSPS, it provides sufficient bandwidth to digitize 70+ MHz IF signals for FFT-based spectral analysis. The high SFDR at high input frequencies - documented in TI's ADS548x datasheet - preserves weak-sidelobe detection near strong carriers. The 5V/3.3V split supply simplifies integration with legacy analog front ends.
Recommended
Recommended Products Summary
Engineering reference data for ADS5484IRGC25 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADS5485IRGC25 | ADS5483IRGCTG4 | ADS5482IRGC25 | ADS5481IRGC25 |
|---|---|---|---|---|---|
| Package | 64-VQFN PowerPAD 9x9 | 64-VQFN PowerPAD 9x9 - same | 64-VQFN PowerPAD 9x9 - same | 64-VQFN PowerPAD 9x9 - same | 64-VQFN PowerPAD 9x9 - same |
| Brand | Texas Instruments | Texas Instruments - same | Texas Instruments - same | Texas Instruments - same | Texas Instruments - same |
| Sample Rate | 170 MSPS | 200 MSPS | 135 MSPS | 105 MSPS | 80 MSPS |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit |
| Analog Supply | 5 V | 5 V | 5 V | 5 V | 5 V |
| Digital Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Digital Output | LVDS | LVDS | LVDS | LVDS | LVDS |
| Process | BiCom3 bipolar | BiCom3 bipolar | BiCom3 bipolar | BiCom3 bipolar | BiCom3 bipolar |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Key Differentiators
- Highest sample rate at 16-bit resolution in the pin-compatible ADS548x family (vs ADS5483IRGCTG4)
- Pin-compatible upgrade path to 200 MSPS within the same footprint (vs ADS5485IRGC25)
- Buffered differential inputs isolate upstream signal chain (vs ADS5481IRGC25)
Design Notes
Estimated: the ADS5484IRGC25 draws approximately 1.3W from the 5V analog supply at 170 MSPS with a 2Vpp input. Bypass each AVDD pin with a 10uF ceramic plus a 0.1uF X7R placed within 5mm of the pin; route the analog and digital ground planes separately and stitch them only under the exposed pad. The 3.3V DRVDD draws approximately 200 mW and should be decoupled with its own 10uF + 0.1uF pair. Use ferrite beads on the analog supply if the upstream 5V regulator is a switching type.
Estimated: at 170 MSPS and full LVDS activity, total power dissipation reaches ~1.7W. The 64-VQFN PowerPAD provides a low-theta_JA thermal path; solder the exposed pad to a 0.5 square inch copper pour with a 4x4 thermal via array (0.3mm drill, 0.5mm pitch) to a ground plane. With proper stitching, junction temperature rise at 85C ambient stays below 30C above ambient, well within the -40C to +85C industrial spec.
Per TI's ADS548x datasheet, route the analog differential inputs (VINP/VINN) as a 100-ohm differential pair with matched length to within 0.5mm, and keep the pair away from the LVDS output bus and clock traces. Place input coupling capacitors directly across the input pins. The clock input (pin 40) is sensitive - route it as a 50-ohm controlled-impedance line from the clock generator with a series ferrite bead if needed. Keep digital output traces length-matched within a byte to preserve LVDS timing margins.
Estimated: LVDS output edges at 170 MSPS have ~300 ps rise time. Use 100-ohm differential impedance for LVDS traces, length-match within 0.13mm (= 25 ps at 5 ps/mm) per nibble, and terminate at the FPGA receiver with a 100-ohm resistor across the pair. Maintain a continuous reference plane under all LVDS traces to control common-mode noise. The exposed pad must be grounded to provide the return path; floating it degrades LVDS eye and increases EMI.
Per TI's datasheet and family documentation, do not exceed the absolute maximum AVDD of 5.5V or DRVDD of 3.6V - damage is permanent. Do not operate the ADS5484IRGC25 without the exposed pad soldered to ground; the thermal path is required for reliability. The ADS5484 and ADS5485 share pinout but differ in sample rate - firmware configuration in the FPGA must match the chosen speed grade. Finally, do not use the internal reference with high-impedance source; the buffered inputs expect a low-impedance driver.
Compliance Information
RoHS compliant per TI product page. Industrial -40C to +85C temperature grade; AEC-Q100 qualification not applicable for this non-automotive ADC family.
