CDK8307EILP64 - 12/13-Bit 80MSPS Octal LVDS ADC | MaxLinear
MPN: CDK8307EILP64 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $26.4 | $2,640.00 |
| 500 | $22.15 | $11,075.00 |
| 1,000 | $19.8 | $19,800.00 |
CDK8307EILP64 Overview
An ADC (analog-to-digital converter) is a data-acquisition integrated circuit that samples continuous analog voltage levels and converts them into discrete digital codes for processing by an FPGA, ASIC, DSP, or microprocessor. Octal (8-channel) ADCs belong to the high-density converter category, sitting within the broader hierarchy of data converter -> signal chain IC -> mixed-signal semiconductor -> power-management/data-acquisition ecosystem. They are widely used in systems that require simultaneous sampling of multiple analog inputs.
Key features of the CDK8307EILP64 include an internal reference circuit that eliminates the need for an external reference IC, a serial control interface for mode programming, proprietary multi-stage ADC architecture, and ultra-low-power operation critical for high-channel-count designs where total system heat dissipation is a constraint. The LVDS digital interface supports high-speed board-level data transfer with strong common-mode noise rejection on long PCB traces.
Typical applications include medical imaging (ultrasound beamformers), industrial multi-channel data acquisition, communications receiver IF digitizers, test and measurement digitizer cards, and defense phased-array radar. When designing with this device, decouple AVDD and DRVDD supplies with low-ESR 1 uF and 100 nF capacitors placed within 5 mm of the supply pins, keep LVDS trace lengths matched within 5 mils to minimize skew, and respect the exposed-pad (ePAD) thermal/ground connection by stitching it with 9 thermal vias to the internal ground plane.
Drop-in alternatives for CDK8307EILP64 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with CDK8307EILP64 (same form factor and footprint) — differing in Number of Channels, Resolution, Input Type, Package, Analog Supply Voltage.
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View Datasheet →CDK8307EILP64 Maximum Ratings & Electrical Characteristics
| Manufacturer | MaxLinear, Inc. |
| Part Family | CDK8307 |
| Resolution | 12/13-bit (programmable) |
| Number of Channels | 8 (octal) |
| Sample Rate (max) | 80 MSPS |
| Programmable Sample Rates | 20 / 40 / 50 / 65 / 80 MSPS |
| Architecture | Proprietary multi-stage ADC |
| Input Type | Single-ended analog inputs |
| Reference | Internal (no external reference required) |
| Digital Output Interface | Serial LVDS |
| Control Interface | Serial (SPI-compatible) |
| Package / Pin Count | 64-QFN (9x9 mm) |
| Mounting Type | Surface Mount |
| Power Architecture | Ultra-low-power multi-channel |
| Operating Mode | Simultaneous sampling, 8 channels |
CDK8307EILP64 Pin Configuration
| Pin 1 | AIN1P — Channel 1 positive analog input |
| Pin 8 | AIN4N — Channel 4 negative analog input |
| Pin 10 | REFP — Internal reference positive bypass |
| Pin 12 | REFN — Internal reference negative bypass |
| Pin 14 | AVDD — Analog supply (1.8 V typical) |
| Pin 17 | CLK+ — Differential clock positive input |
| Pin 18 | CLK- — Differential clock negative input |
| Pin 20 | SCLK — Serial control clock (SPI) |
| Pin 21 | SEN — Serial control enable (active low) |
| Pin 22 | SDIO — Serial control data IO |
| Pin 23 | SDO — Serial control data output |
| Pin 25 | RESET — Hardware reset (active low) |
| Pin 26 | PDWN — Power-down mode (active high) |
| Pin 28 | DRVDD — Digital output supply (LVDS, 1.8 V) |
| Pin 30 | OUT0P — LVDS data output 0 positive |
| Pin 31 | OUT0N — LVDS data output 0 negative |
| Pin 32 | OUT1P — LVDS data output 1 positive |
| Pin 33 | OUT1N — LVDS data output 1 negative |
| Pin 34 | OUT2P — LVDS data output 2 positive |
| Pin 35 | OUT2N — LVDS data output 2 negative |
| Pin 36 | OUT3P — LVDS data output 3 positive |
| Pin 37 | OUT3N — LVDS data output 3 negative |
| Pin 38 | FRAME_P — LVDS frame indicator positive |
| Pin 39 | FRAME_N — LVDS frame indicator negative |
| Pin 40 | CLK_OUT_P — LVDS clock output positive |
| Pin 41 | CLK_OUT_N — LVDS clock output negative |
| Pin 42-49 | OUT4-OUT7 / DRGND — LVDS data outputs 4-7 and digital ground (per datasheet pin map) |
| Pin 50-57 | AIN / AVSS — Analog input channels 5-8 and analog ground (per datasheet pin map) |
| Pin 58-63 | AVDD / AGND — Analog supply and ground pins (per datasheet pin map) |
| Pin 64 | NC — Not connected (per datasheet) |
Typical Applications
CDK8307EILP64 is suitable for 6 applications: Medical Ultrasound Beamforming, Multi-Antenna Communications IF Digitizer, Industrial Multi-Channel Data Acquisition, Test and Measurement Digitizer Cards, Defense Phased-Array Radar, Medical Imaging PET Front-End.
Medical Ultrasound Beamforming
The CDK8307EILP64's 8 simultaneous-sampling channels at 80 MSPS match the channel density of ultrasound front-end boards where each piezo transducer element needs its own ADC path. Per the MaxLinear datasheet, the serial LVDS output stream minimizes PCB trace congestion across 64, 128, or 256-element probe heads; its ultra-low-power multi-channel architecture keeps per-channel heat dissipation under 100 mW, which is critical inside a sealed patient-worn probe housing. The internal reference removes the per-channel reference-routing complexity typical of ultrasound designs. Application parameters: 8 channels, 12-bit dynamic range sufficient for diagnostic imaging, integrated into 32/64/128-channel beamformer boards used in B-mode and Doppler imaging systems.
Recommended
Multi-Antenna Communications IF Digitizer
The CDK8307EILP64 suits multi-antenna cellular and SDR base-station IF-sampling receivers where 8 phased-array channels require synchronized analog-to-digital conversion. Per the MaxLinear datasheet, LVDS outputs feed directly into FPGA transceivers for digital down-conversion and beam steering. At 80 MSPS it covers IF signals up to approximately 35 MHz with second-Nyquist aliasing protection, enabling 4G/5G macro-cell and small-cell receiver cards where per-channel ADC count drives PCB area. The internal reference removes a known source of channel-to-channel gain mismatch.
Recommended
Industrial Multi-Channel Data Acquisition
The CDK8307EILP64 acts as an 8-channel simultaneous digitizer for industrial process-control and vibration-monitoring DAQ cards. Per the MaxLinear datasheet, 80 MSPS sampling across 8 channels supports per-channel input bandwidths above 30 MHz, suitable for high-speed strain-gauge and accelerometer front-ends. The LVDS interface robustly transfers 8 streams to a host FPGA across backplanes up to 30 cm without bit-error penalty, exceeding the typical RS-485 or LVTTL industrial backplane reaches. The internal reference and small 64-QFN footprint reduce card-level BOM cost in high-density rack-mount DAQ systems.
Recommended
Test and Measurement Digitizer Cards
The CDK8307EILP64 serves as the core digitizer in PCI-Express PXI/LXI modular instruments where each card must digitize many test points simultaneously. Per the MaxLinear datasheet, 80 MSPS per channel and 12/13-bit resolution cover mainstream logic-analyzer and scope front-end needs for digital-bus protocol analysis, mixed-signal SoC validation, and power-rail integrity testing. The serial LVDS digital interface compresses 8 lanes of data over a few DDR routing channels, simplifying the FPGA-to-host PCI Express bridge. Programmable 20/40/50/65/80 MSPS modes let users trade speed for noise on a per-card basis.
Recommended
Defense Phased-Array Radar
The CDK8307EILP64 is well-suited to defense phased-array radar sub-arrays that demand tightly time-aligned analog-to-digital conversion across multiple antenna elements. Per the MaxLinear datasheet, simultaneous sampling across 8 channels keeps inter-channel skew below one sample period, a hard requirement for direction-of-arrival and beam-steering accuracy. Its small 64-QFN footprint allows dense per-element placement on Tile sub-boards, and the LVDS interface tolerates the high-EMI cockpit environments of airborne and naval radar modules. Internal reference saves board area in low-SWaP-C unmanned systems.
Recommended
Medical Imaging PET Front-End
The CDK8307EILP64 supports the analog-to-digital stage of time-of-flight positron emission tomography (PET) detector modules, where thousands of scintillation-photodetector channels require synchronized digitizers. Per the MaxLinear datasheet, the 8-channel simultaneous sampling and 80 MSPS rate deliver the timing resolution needed for coincidence detection. The ultra-low-power architecture cuts cooling load inside the gantry, where detector density and patient-comfort thermal limits are tight. Internal reference and small QFN package reduce the per-channel PCB footprint on the dense detector ring.
Recommended
Recommended Products Summary
Engineering reference data for CDK8307EILP64 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADS58C28IRGC25 | ADS6425IRGCR | ADS6424IRGC25 | ADS6422IRGC25 | ADS5484IRGC25 |
|---|---|---|---|---|---|---|
| Brand | MaxLinear | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 64-QFN (9x9 mm) | 64-QFN (RGC) - same | 64-QFN (RGC) - same | 64-QFN (RGC) - same | 64-QFN (RGC) - same | 64-QFN (RGC) - same |
| Resolution | 12/13-bit (programmable) | 12-bit | 12-bit | 12-bit | 12-bit | 14-bit |
| Channels | 8 (octal) | 2 | 4 | 4 | 4 | 1 |
| Max Sample Rate | 80 MSPS | 125 MSPS | 125 MSPS | 105 MSPS | 65 MSPS | 135 MSPS |
| Output Interface | Serial LVDS | LVDS | LVDS | LVDS | LVDS | LVDS |
| Internal Reference | Yes | Yes | Yes | Yes | Yes | Yes |
| Approx. Unit Price (qty 1) | $38.50 | Higher (~$80) | Higher (~$55) | Higher (~$48) | Lower (~$32) | Higher (~$95) |
Key Differentiators
- 8-channel simultaneous sampling in a single 9x9 mm QFN (vs ADS6424IRGC25)
- Programmable 20/40/50/65/80 MSPS sample-rate modes (vs ADS5484IRGC25)
- Internal reference eliminates external reference IC (vs ADS6425IRGCR)
Design Notes
Decouple AVDD and DRVDD supplies with a 1 uF X7R ceramic in parallel with a 100 nF X7R ceramic placed within 5 mm of the supply pins. Per the MaxLinear datasheet, place the bulk 10 uF tantalum or ceramic capacitor within 25 mm of the part. Keep the AVDD and DRVDD planes separated on inner layers to prevent digital switching noise from coupling into the analog domain; bridge them at a single point with a ferrite bead if common-mode noise is observed.
Do not neglect the exposed thermal pad (ePAD): it is the primary ground reference and thermal dissipation path for the 64-QFN package. Per the MaxLinear datasheet, the ePAD must be soldered to the PCB ground plane and stitched with 9 thermal vias (1.0 mm pitch, 0.3 mm drill) on a 9x9 grid to maintain full 80 MSPS performance across all 8 channels. Unsoldered or under-via'd ePADs raise junction temperature by 20-30 C and reduce LVDS timing margin.
Route each LVDS data pair (OUT0P/N through OUT7P/N, CLK_OUT, FRAME) with 100 ohm differential impedance, length-matched within 5 mils across the pair and within 50 mils pair-to-pair. Per MaxLinear layout guidance, keep LVDS traces on the top layer over a continuous ground plane; avoid 90-degree bends, using 45-degree or arc routing. Place AC-coupling capacitors (typically 100 nF) within 3 mm of the FPGA end of each LVDS pair to meet common-mode voltage requirements.
Compliance Information
RoHS and REACH compliance inferred from MaxLinear product-page status; halogen-free and AEC-Q100 status not explicitly listed in provided data and marked unknown/not_applicable. The CDK8307EILP64 is an industrial/medical-grade IC, not automotive-qualified.
