ADS61B49IRGZ25 - 14-Bit 250MSPS Buffered ADC | Texas Instruments
MPN: ADS61B49IRGZ25 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.95 | $2,895.00 |
| 500 | $24.4 | $12,200.00 |
| 1,000 | $21.1 | $21,100.00 |
ADS61B49IRGZ25 Overview
An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that converts continuous analog waveforms into discrete digital codes at a defined sample rate. Pipelined ADCs use a multi-stage architecture to achieve high sample rates (hundreds of MSPS) with moderate resolution (10-16 bits), occupying a position in the signal chain hierarchy: sensor/buffer -> variable-gain amplifier -> ADC -> DSP/FPGA. The ADS61B49 belongs to TI's ADS61xx family of buffered-input, low-power data converters used in communications, test equipment, and industrial imaging.
Key specifications include 14-bit resolution, 250 MSPS maximum sample rate, internal references eliminating the need for external reference decoupling capacitors, parallel/LVDS output interface, and an integrated input buffer that handles high source-impedance sensors directly. The 48-VQFN package provides an exposed thermal pad for low thermal resistance, supporting reliable operation across the full industrial temperature range.
Architecturally, the device uses a multi-stage pipelined core with on-chip sample-and-hold and internal bandgap references. The input buffer isolates the switched-capacitor sampling front-end from external drive circuitry, improving SFDR/SNR performance when the source impedance is non-zero. The internal references remove layout sensitivity around external reference pins, a common pitfall in high-speed ADC designs.
Typical applications include communications test equipment, multi-carrier GSM/UMTS/LTE base-station receivers, medical imaging front-ends, industrial ultrasound, and high-speed data acquisition systems. The buffered input makes it particularly suitable for direct connection to differential IF stages without an external op-amp driver.
When designing with this device, allocate sufficient PCB area for the thermal pad and stitch vias to inner ground planes; route LVDS outputs with controlled 100-ohm differential impedance; and place input coupling capacitors and common-mode bias resistors as close to the analog input pins as the layout allows. Use a quiet, low-noise LDO such as the TPS7A4701 on the AVDD rail to maximize SFDR.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet. It is intended to accelerate sourcing and first-pass PCB decisions for engineers specifying a 250 MSPS buffered-input ADC.
Drop-in alternatives for ADS61B49IRGZ25 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADS61B49IRGZ25 (same form factor and footprint) — differing in Operating Temperature Range, Package, Resolution, Analog Supply Voltage, Input Type.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADS61B49IRGZT
✅ Drop-In📋 Reference alternative (not in catalog)
ADS61B49IRGZR
✅ Drop-In📋 Reference alternative (not in catalog)
ADS61B29IRGZ25
✅ Drop-In✓ In Stock
$17.8 / Unit
View Datasheet →ADS6129IRGZ25
✅ Drop-In✓ In Stock
$23.1 / Unit
View Datasheet →ADS62P23IRGC25
✅ Drop-In✓ In Stock
$18.85 / Unit
View Datasheet →ADS61B49IRGZ25 Maximum Ratings & Electrical Characteristics
| Resolution | 14 bit |
| Sample Rate (Max) | 250 MSPS |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Analog Input Type | Buffered, differential |
| Data Interface | Parallel / LVDS |
| Reference Type | Internal (no external ref pins) |
| Analog Supply Voltage | 1.8 V (typ) |
| Digital Supply Voltage | 1.8 V to 3.3 V |
| Operating Temperature Range | -40 C to +85 C |
| Package | 48-pin VQFN (RGZ) 7x7 mm with EP |
| Mounting Type | Surface Mount |
| MSL Level | 3 (168 hours) |
| RoHS Status | Compliant |
ADS61B49IRGZ25 Pin Configuration
| Pin 1 | INP — Positive analog input (differential) |
| Pin 2 | INM — Negative analog input (differential) |
| Pin 3 | VCM — Common-mode voltage output (bias for input coupling) |
| Pin 4 | AVDD — Analog supply, 1.8 V |
| Pin 5 | AGND — Analog ground |
| Pin 6 | CLK — Sampling clock input (differential) |
| Pin 7 | CLKM — Sampling clock input complement |
| Pin 8 | DRVDD — Digital output driver supply, 1.8 V to 3.3 V |
| Pin 9 | DRGND — Digital output driver ground |
| Pin 10 | D[0] — LVDS/parallel data output bit 0 |
| Pin 11 | D[1] — LVDS/parallel data output bit 1 |
| Pin 12 | D[2] — LVDS/parallel data output bit 2 |
| Pin 13 | D[3] — LVDS/parallel data output bit 3 |
| Pin 14 | D[4] — LVDS/parallel data output bit 4 |
| Pin 15 | D[5] — LVDS/parallel data output bit 5 |
| Pin 16 | D[6] — LVDS/parallel data output bit 6 |
| Pin 17 | D[7] — LVDS/parallel data output bit 7 |
| Pin 18 | D[8] — LVDS/parallel data output bit 8 |
| Pin 19 | D[9] — LVDS/parallel data output bit 9 |
| Pin 20 | D[10] — LVDS/parallel data output bit 10 |
| Pin 21 | D[11] — LVDS/parallel data output bit 11 |
| Pin 22 | D[12] — LVDS/parallel data output bit 12 |
| Pin 23 | D[13] — LVDS/parallel data output bit 13 |
| Pin 24 | DCLK — LVDS/parallel data clock output |
| Pin 25 | FCLK — LVDS frame clock output |
| Pin 26 | AGND — Analog ground |
| Pin 27 | AVDD — Analog supply, 1.8 V |
| Pin 28 | NC — Not connected (per datasheet) |
| Pin 29 | SEN — Serial interface enable |
| Pin 30 | SDATA — Serial interface data |
| Pin 31 | SCLK — Serial interface clock |
| Pin 32 | RESET — Hardware reset, active low |
| Pin 33 | PDN — Power-down, active high |
| Pin 34 | AVDD — Analog supply, 1.8 V |
| Pin 35 | AGND — Analog ground |
| Pin 36 | AVDD — Analog supply, 1.8 V |
| Pin 37 | AGND — Analog ground |
| Pin 38 | NC — Not connected (per datasheet) |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | AVDD — Analog supply, 1.8 V |
| Pin 41 | AGND — Analog ground |
| Pin 42 | AVDD — Analog supply, 1.8 V |
| Pin 43 | AGND — Analog ground |
| Pin 44 | NC — Not connected (per datasheet) |
| Pin 45 | NC — Not connected (per datasheet) |
| Pin 46 | AVDD — Analog supply, 1.8 V |
| Pin 47 | AGND — Analog ground |
| Pin 48 | EP — Exposed thermal pad - must be soldered to AGND pour with thermal vias |
Typical Applications
ADS61B49IRGZ25 is suitable for 6 applications: Communications Test Equipment, Multi-Carrier Wireless Base-Station Receiver, Medical Ultrasound Imaging Front-End, Industrial High-Speed DAQ Module, Software-Defined Radio (SDR) Front-End, Radar and Lidar Signal Acquisition.
Communications Test Equipment
The ADS61B49IRGZ25's 14-bit resolution at 250 MSPS makes it well-suited for digitizing wideband IF signals in bench-top spectrum analyzers, signal generators, and modular instrumentation. The integrated analog input buffer allows direct connection to the IF output of a mixer without an external op-amp driver, reducing the front-end bill of materials and improving SFDR at high source impedances. Engineers route the LVDS data into an FPGA for FFT-based demodulation, achieving sufficient spurious-free dynamic range to characterize adjacent-channel leakage in production-line LTE and 5G NR transmitter tests.
Recommended
Multi-Carrier Wireless Base-Station Receiver
In multi-carrier GSM, UMTS, and LTE base-station receiver chains, the ADS61B49IRGZ25 digitizes intermediate-frequency signals carrying multiple adjacent carriers simultaneously. The 250 MSPS sample rate provides oversampling headroom for digital filtering and decimation, while the 14-bit resolution delivers adequate dynamic range for crest-factor management of aggregated carrier waveforms. The internal references and buffered input reduce PCB area, enabling compact remote-radio-head (RRH) designs where board real estate and thermal density are critical.
Recommended
Medical Ultrasound Imaging Front-End
Diagnostic ultrasound systems digitize phased-array transducer channels at high sample rates to support beamforming and Doppler processing. The ADS61B49IRGZ25's integrated analog input buffer handles the high-impedance piezoelectric transducer signals directly, eliminating per-channel external drivers that would otherwise dominate PCB area and BOM cost across the 64- to 128-channel arrays. At 250 MSPS with 14 bits, the ADC delivers sufficient time-domain resolution for harmonic imaging modes used in cardiac and vascular diagnostics.
Recommended
Industrial High-Speed DAQ Module
Modular data-acquisition systems for vibration analysis, machine-condition monitoring, and radar digitizing benefit from the ADS61B49IRGZ25's combination of 250 MSPS sample rate, 14-bit resolution, and integrated buffer. The buffered input tolerates long cable runs to piezoelectric accelerometers and IEPE sensors without external driver stages. The internal references eliminate trimming procedures, simplifying factory calibration in high-volume industrial DAQ module production lines used for predictive-maintenance installations.
Recommended
Software-Defined Radio (SDR) Front-End
Wideband software-defined radio platforms for spectrum monitoring, electronic warfare training, and amateur-radio transceivers require ADCs that can capture large instantaneous bandwidths. The ADS61B49IRGZ25's 250 MSPS sample rate supports roughly 100 MHz of usable Nyquist-bandwidth capture per channel, while its 14-bit resolution preserves dynamic range against in-band interferers. The buffered input connects directly to common SDR front-end mixer outputs, simplifying the analog chain between antenna, LNA, mixer, and ADC.
Recommended
Radar and Lidar Signal Acquisition
Automotive and industrial radar systems, plus automotive lidar receivers, digitize IF or baseband chirp returns at high sample rates for range-Doppler processing. The ADS61B49IRGZ25 supports a single-channel 250 MSPS acquisition path for short-range (<60 GHz) radar front-ends. Its industrial -40 C to +85 C temperature range and 48-VQFN package suit the harsh thermal environment of automotive ADAS sensor modules, where compact PCB layout and AEC-Q-qualified parts are required by tier-1 OEM specifications.
Recommended
Recommended Products Summary
Engineering reference data for ADS61B49IRGZ25 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADS61B49IRGZT | ADS61B49IRGZR | ADS61B29IRGZ25 | ADS6129IRGZ25 | ADS62P23IRGC25 |
|---|---|---|---|---|---|---|
| Package | 48-VQFN (RGZ) 7x7 mm | 48-VQFN (RGZ) - same | 48-VQFN (RGZ) - same | 48-VQFN (RGZ) - same | 48-VQFN (RGZ) - same | 48-VQFN (RGZ) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 14 bit | 14 bit | 14 bit | 12 bit | 12 bit | 12 bit |
| Max Sample Rate | 250 MSPS | 250 MSPS | 250 MSPS | 250 MSPS | 125/210 MSPS (family) | 80/105 MSPS per channel (dual) |
| Number of Channels | 1 | 1 | 1 | 1 | 1 | 2 |
| Input Buffer | Integrated | Integrated | Integrated | Integrated | Integrated | Integrated |
| Reference Type | Internal | Internal | Internal | Internal | Internal | Internal |
| Output Interface | Parallel / LVDS | Parallel / LVDS | Parallel / LVDS | Parallel / LVDS | Parallel / LVDS | Parallel / LVDS |
| Automotive Grade (AEC-Q100) | No (Industrial) | No (Industrial) | No (Industrial) | No (Industrial) | No (Industrial) | No (Industrial) |
| Approx. Unit Price (USD, qty 1) | 38.50 | 38.50 | 38.50 | lower | lower | lower |
Key Differentiators
- Integrated analog input buffer eliminates external driver op-amp (vs ADS62P48IRGC25 (dual-channel, 14-bit, 250 MSPS))
- 14-bit resolution at 250 MSPS in a single-channel pin-compatible family (vs ADS61B29IRGZ25 (12-bit sibling))
- Internal references - no external reference pins (vs ADS5484IRGC25 (16-bit, 170 MSPS, external ref pins))
- Same 48-VQFN package across the 14-bit, 12-bit, and lower-speed siblings (vs ADS6129IRGZ25 (lower-speed family member))
Design Notes
The 48-VQFN (RGZ) exposed thermal pad must be soldered to a continuous analog-ground copper pour with a 4x4 (minimum) grid of 0.3 mm thermal vias stitching to inner ground planes. Per the TI datasheet layout section, this provides both the ground reference for the input buffer and the primary thermal path; deleting the EP soldering compromises both electrical and thermal performance. Place input-coupling capacitors and the VCM common-mode bypass within 2 mm of the INP/INM pins.
Power the AVDD rail with a low-noise LDO such as the TPS7A4701RGWR; a switching converter introduces wideband noise that couples into the input buffer and degrades SFDR by 5-10 dB. Place a 10 uF X7R ceramic plus a 0.1 uF NP0/C0G bypass within 1 mm of each AVDD pin. The DRVDD rail can tolerate a switching converter if pi-filtered, since output-domain supply noise couples only through the LVDS driver stage.
Route the LVDS data outputs (D[0:13], DCLK, FCLK) with 100-ohm differential impedance and keep traces length-matched within 1 mm (5 ps) to avoid inter-pair skew. The ADC's internal serializer determines the LVDS eye; route adjacent LVDS pairs on the same layer with a continuous reference-ground plane underneath. Match the differential CLK/CLKM input pair within 1 mm to preserve the sampling instant and minimize aperture jitter.
Do not assume the input buffer eliminates source-impedance matching; for best SFDR, drive INP/INM through a wideband transformer (e.g., ADT1-1WT) or a balun with a defined source impedance. Avoid routing digital LVDS signals across the analog INP/INM traces on any layer, including inner layers split under the ADC - they will couple spurs into the input. If using the serial interface (SDATA/SCLK/SEN), tie SDATA low during reset to prevent latch-up of the configuration register.
Compliance Information
RoHS and REACH compliant per TI product page; lead-free (Pb-free) terminal finish; not AEC-Q100 qualified - industrial temperature grade only (-40C to +85C).
