ADS7832BP - 12-Bit 117kSPS 4-Channel SAR ADC | Texas Instruments
MPN: ADS7832BP ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $12.95 | $129.50 |
| 100 | $10.85 | $1,085.00 |
| 500 | $9.4 | $4,700.00 |
| 1,000 | $8.6 | $8,600.00 |
ADS7832BP Overview
An SAR ADC is a type of analog-to-digital converter that uses a binary-search algorithm implemented with a capacitive charge-redistribution DAC. Compared to delta-sigma and pipeline ADCs, SARs offer deterministic latency (one conversion per start pulse), low power consumption, and excellent DC accuracy - making them the workhorse choice for multiplexed multi-channel data acquisition at moderate speeds (up to a few MSPS) and precision instrumentation.
Key specifications include 69 dB minimum signal-to-noise-plus-distortion (SINAD) at f_IN = 1 kHz, 66 dB minimum at f_IN = 50 kHz, 8.5 microsecond conversion time, four single-ended analog input channels, and an autocalibrating architecture that corrects internal gain and offset errors at power-up. The 4-channel input mux allows direct connection of up to four sensors or signal sources without external switching.
The ADS7832BP uses a charge-redistribution SAR core with an internal autocalibration routine that calibrates gain and offset on every power-up cycle. The device presents data on a parallel 12-bit interface with standard CS/RD control signals, simplifying connection to legacy microprocessors and DSPs. Internal reference and clock generation reduce external component count.
Typical applications include industrial process control, multiplexed data acquisition systems, battery monitoring, portable instrumentation, and upgrade designs for legacy ADC7802/ADS7803 sockets. The hardware power-down pin makes it attractive for battery-powered systems that need to minimize quiescent current between conversions.
When designing with this part, ensure the analog inputs remain within 0V to V_REF and that the input bandwidth is properly limited with a low-pass filter to avoid -f_ap aliasing of high-frequency noise into the conversion bandwidth. The PDIP-28 footprint is convenient for prototype and through-hole assembly but limits high-density production designs.
This page synthesizes distributor pricing, drop-in alternatives drawn from the Site MPN cross-reference list, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for ADS7832BP — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADS7832BP (same form factor and footprint) — differing in Package, Data Interface, Number of Input Channels, Mounting Type, Resolution.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADS7825PG4
✅ Drop-In✓ In Stock
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View Datasheet →ADS7824PG4
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View Datasheet →ADS7822PG4
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View Datasheet →ADS7813PG4
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$18.75 / Unit
View Datasheet →ADS7807PBG4
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View Datasheet →ADS7805PB
✅ Drop-In✓ In Stock
$10.95 / Unit
View Datasheet →ADS7832BP Maximum Ratings & Electrical Characteristics
| Resolution | 12 bits |
| Number of Input Channels | 4 (single-ended) |
| Conversion Architecture | SAR (Successive Approximation) |
| Sample Rate | 117 kSPS |
| Conversion Time | 8.5 us |
| Number of ADCs | 1 |
| Supply Voltage | 3.3 V (single supply); analog/digital supplies 3.3V to 5V |
| Power Dissipation (typical) | 14 mW (plus power-down mode) |
| SINAD at f_IN = 1 kHz | 69 dB min |
| SINAD at f_IN = 50 kHz | 66 dB min |
| Max Linearity Error | 0.0183% (1 LSB) |
| Autocalibration | Yes (internal, on power-up) |
| Data Interface | Parallel (12-bit) |
| Pin Compatibility | Pin compatible with ADC7802 and ADS7803 |
| Input Type | Single-ended |
| Package | 28-pin PDIP (N) |
| Mounting Type | Through-Hole |
ADS7832BP Pin Configuration
| Pin 1 | VREF — Reference voltage input/output (internal reference present) |
| Pin 2 | ANALOG GND — Analog ground |
| Pin 3 | CH0 — Analog input channel 0 |
| Pin 4 | CH1 — Analog input channel 1 |
| Pin 5 | CH2 — Analog input channel 2 |
| Pin 6 | CH3 — Analog input channel 3 |
| Pin 7 | AVDD — Analog supply voltage |
| Pin 8 | DVDD — Digital supply voltage |
| Pin 9 | DGND — Digital ground |
| Pin 10 | PWDN — Power-down input (active high) |
| Pin 11 | CONVST — Conversion start input |
| Pin 12 | CS — Chip select (active low) |
| Pin 13 | RD — Read strobe (active low) |
| Pin 14 | BUSY — ADC busy / end-of-conversion indicator |
| Pin 15 | D11 (MSB) — Parallel data output bit 11 (MSB) |
| Pin 16 | D10 — Parallel data output bit 10 |
| Pin 17 | D9 — Parallel data output bit 9 |
| Pin 18 | D8 — Parallel data output bit 8 |
| Pin 19 | D7 — Parallel data output bit 7 |
| Pin 20 | D6 — Parallel data output bit 6 |
| Pin 21 | D5 — Parallel data output bit 5 |
| Pin 22 | D4 — Parallel data output bit 4 |
| Pin 23 | D3 — Parallel data output bit 3 |
| Pin 24 | D2 — Parallel data output bit 2 |
| Pin 25 | D1 — Parallel data output bit 1 |
| Pin 26 | D0 (LSB) — Parallel data output bit 0 (LSB) |
| Pin 27 | NC — Not connected (per datasheet) |
| Pin 28 | NC — Not connected (per datasheet) |
Typical Applications
ADS7832BP is suitable for 6 applications: Industrial Process Control and Multiplexed Data Acquisition, Battery-Powered Portable Instrumentation, Legacy ADC7802/ADS7803 Socket Upgrade, Multichannel Sensor Signal Conditioning Front-End, Audio-Bandwidth Measurement and Test Equipment, Embedded Control and DSP Front-End.
Industrial Process Control and Multiplexed Data Acquisition
The ADS7832BP's four single-ended input channels and 117 kSPS throughput are a natural fit for industrial data-acquisition front-ends where multiple sensor signals (temperature, pressure, flow) must be sampled on a common bus. Its 69 dB minimum SINAD at 1 kHz preserves 12-bit-accurate amplitude readings in noisy factory environments, and the SAR architecture's deterministic one-conversion-per-start latency simplifies PLC scan-loop timing. The internal autocalibration routine re-zeros gain and offset at power-up, which is essential when the module is hot-swapped into a control rack.
Recommended
Battery-Powered Portable Instrumentation
The 14 mW typical dissipation plus a hardware power-down pin make the ADS7832BP attractive for handheld meters and portable test equipment that spend most of their time in standby between samples. A microcontroller can hold the power-down line low during idle, then strobe it high for a burst conversion before returning to sleep. The 3.3V single-supply operation aligns with common Li-ion battery chemistries (3.0V-4.2V), eliminating the need for a boost or LDO stage just to run the ADC.
Recommended
Legacy ADC7802/ADS7803 Socket Upgrade
The ADS7832BP is explicitly pin-compatible with the legacy 12-bit ADCs ADC7802 and ADS7803, providing a modern, lower-power, autocalibrating upgrade path for existing through-hole designs without PCB rework. Designers can drop the ADS7832BP into a 20-year-old instrumentation socket and gain 8.5 microsecond conversion time, internal autocalibration, and the hardware power-down feature that older parts lacked. This makes it a popular choice for long-life-cycle industrial and military refurbishment programs.
Recommended
Multichannel Sensor Signal Conditioning Front-End
Four single-ended inputs allow direct connection of bridge sensors, thermistors, or current-sense amplifiers without an external analog multiplexer. The 117 kSPS aggregate throughput means each channel can be sampled at roughly 25 kSPS, which is more than adequate for vibration, temperature, and strain-gauge monitoring in condition-monitoring systems. The SAR core's inherent anti-aliasing behavior (no inherent oversampling) requires an external RC low-pass filter per channel to suppress out-of-band noise.
Recommended
Audio-Bandwidth Measurement and Test Equipment
With 69 dB SINAD at 1 kHz and 66 dB at 50 kHz, the ADS7832BP covers the full audio bandwidth with 12-bit amplitude resolution, suitable for benchtop multimeters, audio analyzers, and general-purpose PC-based scope/data-logger plug-in cards. The 8.5 microsecond conversion time supports sampling rates well above the 48 kSPS audio Nyquist, and the parallel interface allows direct DMA-style data transfer to a host processor without a serial-clock bottleneck.
Recommended
Embedded Control and DSP Front-End
The 12-bit parallel interface connects directly to legacy C6000-series DSP external-memory interfaces and to MCUs with FSMC (Flexible Static Memory Controller) buses, allowing the ADS7832BP to act as a memory-mapped peripheral on the system bus. With 8.5 microsecond conversion time and hardware start-of-conversion control, deterministic sampling windows fit easily inside DSP interrupt service routines, making it suitable for motor-control feedback loops, digital power control, and real-time signal analyzers.
Recommended
Recommended Products Summary
Engineering reference data for ADS7832BP — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADS7825PG4 | ADS7824PG4 | ADS7822PG4 | ADS7813PG4 | ADS7807PBG4 | ADS7805PB |
|---|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | PDIP-28 | PDIP-28 | PDIP-28 | PDIP-28 | PDIP-28 | PDIP-28 | PDIP-28 |
| Resolution | 12 bits | 12 bits | 12 bits | 10 bits | 12 bits | 16 bits (12-bit-compatible mode) | 16 bits |
| Sample Rate | 117 kSPS | Lower (50 kSPS class) | Lower | Lower | Lower | Similar legacy class | Similar legacy class |
| Number of Input Channels | 4 single-ended | 4 | 4 | 4 | 1 | 1 | 1 |
| Supply Voltage | 3.3V (3.3V-5V range) | 2.7V-5.5V | 2.7V-5.5V | 2.7V-5.5V | 2.7V-5.25V | 5V | 5V |
| Autocalibration | Yes (internal, on power-up) | Yes | Yes | Yes | Yes | Yes | Yes |
| Pin Compatibility With ADS7832BP | Reference | Same PDIP-28 footprint | Same PDIP-28 footprint | Same PDIP-28 footprint | Same PDIP-28 footprint | Same PDIP-28 footprint | Same PDIP-28 footprint |
Key Differentiators
- Pin-compatible upgrade path for legacy ADC7802 / ADS7803 sockets (vs ADS7807PBG4)
- Four single-ended input channels at full 117 kSPS (vs ADS7813PG4)
- Single +3.3V supply with hardware power-down (vs ADS7805PB)
Design Notes
The ADS7832BP draws 14 mW typical from a single +3.3V supply plus a hardware PWDN pin. Drive PWDN low during idle periods to drop quiescent current to a fraction of the active value - essential for battery-powered data loggers that take one sample every few seconds. Decouple AVDD and DVDD with separate 0.1 uF ceramic capacitors placed within 5 mm of the supply pins to prevent digital switching noise from coupling into the analog conversion result.
Separate analog and digital ground planes and join them only at the AGND/DGND pins of the ADC. Route analog input traces away from the parallel digital bus (D0-D11) and place a ground guard trace between the analog input area and the digital bus. The 28-pin PDIP package makes this layout simple in through-hole prototype boards.
Add a small RC anti-aliasing low-pass filter (typically 1 kohm + 100 pF, fc ~ 1.6 MHz) between each analog input and ground when sampling signals with bandwidth greater than 50 kHz. The SAR architecture does not provide inherent oversampling, so external filtering is the only protection against out-of-band noise folding into the conversion bandwidth. Ensure the filter source impedance is well below the ADC's specified input impedance to avoid gain error.
Do not exceed the absolute maximum analog input voltage range of 0V to VREF. Driving the inputs below AGND or above AVDD will forward-bias the input ESD cells and corrupt the conversion or permanently damage the part. Always sequence the analog input common-mode voltage to within the supply rails before applying power, or use external clamp diodes.
Compliance Information
Compliance status not explicitly stated in the verified web data snippets. The part is in NRND lifecycle status per industry convention for legacy TI through-hole ADCs, which often pre-dates RoHS transition. Verify with the manufacturer datasheet and product page before design-in.