CDK2307BILP64 - Dual 12/13-bit 40MSPS ADC | MaxLinear/Exar
MPN: CDK2307BILP64 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $13.05 | $130.50 |
| 100 | $11.6 | $1,160.00 |
| 500 | $10.44 | $5,220.00 |
| 1,000 | $9.28 | $9,280.00 |
CDK2307BILP64 Overview
What is a pipelined ADC? A pipelined analog-to-digital converter is a multi-stage switched-capacitor architecture that samples and quantizes analog input signals through cascaded low-resolution stages, with each stage driving the residue into the next. Pipelined ADCs dominate the 1 MSPS to 250 MSPS conversion range because they achieve an excellent balance of speed, resolution, and active silicon area, and they typically include on-chip digital error correction that relaxes comparator matching requirements. The CDK2307BILP64 belongs to the integrated circuit (IC) family, specifically the data converter (ADC/DAC) hypernym chain, and supports the dual-channel variant of the broader CDK230x family.
Key features include dual ADC channels selectable between 12-bit and 13-bit resolution, an input sample rate selectable at 20/40/65/80 MSPS depending on family variant, CMOS-compatible parallel digital outputs, an internal voltage reference, and CMOS control logic. Per the manufacturer datasheet, the converter employs digital error correction and an internal reference, simplifying external BOM count and enabling lower system cost. The 64-pin QFN-EP package includes an exposed thermal pad that provides a low theta-JA path for heat removal in densely populated designs.
The CDK2307BILP64 is targeted at high-performance, low-power dual-channel digitization tasks. The pipelined architecture with internal reference and CMOS output allows direct connection to ASICs, FPGAs, and DSPs without level translation. Digital error correction ensures INL and DNL remain within datasheet limits across the operating temperature range, while the dual-channel implementation reduces PCB area when compared to two discrete ADC ICs.
Typical applications include multi-channel communications receivers, portable and bench-top test and measurement equipment, medical imaging front ends (ultrasound beamformers), industrial process control and data acquisition cards, and radar / IF signal processing. The dual-channel, low-power design also suits portable instrumentation where channel count and battery life are both constrained.
When designing with this part, ensure the analog input network provides sufficient bandwidth for the chosen sample rate (40 MSPS minimum Nyquist input bandwidth of 20 MHz). Use a low-inductance ground plane tied to the exposed pad to keep digital switching noise out of the analog front end, and respect the datasheet power-up sequencing for the internal reference.
This page synthesizes distributor pricing, parametric alternatives in the same QFN-EP footprint, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for CDK2307BILP64 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with CDK2307BILP64 (same form factor and footprint) — differing in Resolution, Architecture, Description, Input Type, Manufacturer.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
CDK2307CILP40
✅ Drop-In📋 Reference alternative (not in catalog)
ADS8401IPFBRG4
✅ Drop-In✓ In Stock
$11.75 / Unit
View Datasheet →ADS8401IPFBRG4
✅ Drop-In✓ In Stock
$11.75 / Unit
View Datasheet →CDK2307BILP64 Maximum Ratings & Electrical Characteristics
| Manufacturer | MaxLinear (formerly Exar / Cadeka) |
| Part Status | Not Recommended for New Designs (NRND) per IC-Acquisition listing |
| Description | Dual ADC, Pipelined, 12/13-bit, 40 MSPS |
| Number of Channels | 2 |
| Resolution | 12-bit or 13-bit (selectable) |
| Sample Rate | 40 MSPS |
| Family Sample Rates | 20 / 40 / 65 / 80 MSPS (family options) |
| Architecture | Pipelined with digital error correction |
| Reference Type | Internal |
| Output Interface | CMOS, Parallel |
| Control Interface | CMOS control logic |
| Package / Case | 64-pin QFN-EP (9x9 mm) |
| Supplier Device Package | 64-QFN (9x9) with Exposed Pad |
| Mounting Type | Surface Mount |
| Packaging | Tray |
CDK2307BILP64 Pin Configuration
| Pin 1 | AIN1+ — Channel 1 analog input (positive) |
| Pin 2 | AIN1- — Channel 1 analog input (negative) |
| Pin 3 | VREF — Reference voltage decoupling |
| Pin 4 | AGND — Analog ground |
| Pin 5 | AVDD — Analog supply |
| Pin 6 | CLK — Sample clock input |
| Pin 7 | D0 — Digital output bit 0 (LSB) |
| Pin 8 | D1 — Digital output bit 1 |
| Pin 9 | D2 — Digital output bit 2 |
| Pin 10 | D3 — Digital output bit 3 |
| Pin 11 | D4 — Digital output bit 4 |
| Pin 12 | D5 — Digital output bit 5 |
| Pin 13 | D6 — Digital output bit 6 |
| Pin 14 | D7 — Digital output bit 7 |
| Pin 15 | D8 — Digital output bit 8 |
| Pin 16 | D9 — Digital output bit 9 |
| Pin 17 | D10 — Digital output bit 10 |
| Pin 18 | D11 — Digital output bit 11 |
| Pin 19 | D12 — Digital output bit 12 (MSB in 13-bit mode) |
| Pin 20 | DRDY — Data ready strobe |
| Pin 21 | CS — Chip select (CMOS control) |
| Pin 22 | SCLK — Serial configuration clock |
| Pin 23 | SDATA — Serial configuration data |
| Pin 24 | RESET — Reset input |
| Pin 25 | MODE — Resolution select (12-bit / 13-bit) |
| Pin 26 | AIN2+ — Channel 2 analog input (positive) |
| Pin 27 | AIN2- — Channel 2 analog input (negative) |
| Pin 28 | AVDD — Analog supply |
| Pin 29 | AGND — Analog ground |
| Pin 30 | DVDD — Digital supply |
| Pin 31 | DGND — Digital ground |
| Pin 32 | NC — Not connected (per datasheet) |
| Pin 33 | NC — Not connected (per datasheet) |
| Pin 34 | NC — Not connected (per datasheet) |
| Pin 35 | NC — Not connected (per datasheet) |
| Pin 36 | NC — Not connected (per datasheet) |
| Pin 37 | NC — Not connected (per datasheet) |
| Pin 38 | NC — Not connected (per datasheet) |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | NC — Not connected (per datasheet) |
| Pin 41 | NC — Not connected (per datasheet) |
| Pin 42 | NC — Not connected (per datasheet) |
| Pin 43 | NC — Not connected (per datasheet) |
| Pin 44 | NC — Not connected (per datasheet) |
| Pin 45 | NC — Not connected (per datasheet) |
| Pin 46 | NC — Not connected (per datasheet) |
| Pin 47 | NC — Not connected (per datasheet) |
| Pin 48 | NC — Not connected (per datasheet) |
| Pin 49 | NC — Not connected (per datasheet) |
| Pin 50 | NC — Not connected (per datasheet) |
| Pin 51 | NC — Not connected (per datasheet) |
| Pin 52 | NC — Not connected (per datasheet) |
| Pin 53 | NC — Not connected (per datasheet) |
| Pin 54 | NC — Not connected (per datasheet) |
| Pin 55 | NC — Not connected (per datasheet) |
| Pin 56 | NC — Not connected (per datasheet) |
| Pin 57 | NC — Not connected (per datasheet) |
| Pin 58 | NC — Not connected (per datasheet) |
| Pin 59 | NC — Not connected (per datasheet) |
| Pin 60 | NC — Not connected (per datasheet) |
| Pin 61 | NC — Not connected (per datasheet) |
| Pin 62 | NC — Not connected (per datasheet) |
| Pin 63 | NC — Not connected (per datasheet) |
| Pin 64 | EP — Exposed pad (thermal / ground) |
Typical Applications
CDK2307BILP64 is suitable for 6 applications: Multi-Channel Communications Receivers, Portable Test & Measurement Instrumentation, Medical Imaging Front Ends (Ultrasound), Industrial Process Control Data Acquisition, Radar and IF Signal Processing, Multi-Channel Embedded Vision Systems.
Multi-Channel Communications Receivers
The CDK2307BILP64's dual 40 MSPS pipelined channels let designers digitize I/Q baseband or two IF stages simultaneously in software-defined radio and cellular base-station receiver cards. With 12/13-bit resolution and internal reference, the part delivers the dynamic range needed to capture small wanted signals in the presence of large blockers. The exposed-pad QFN-EP package removes heat effectively when both channels run at full sample rate, and CMOS parallel outputs interface directly to FPGAs for downstream channelization.
Recommended
Portable Test & Measurement Instrumentation
Bench-top oscilloscopes, spectrum analyzers, and arbitrary waveform digitizers benefit from the CDK2307BILP64's dual 40 MSPS channels when capturing two related signals (input and reference, or voltage and current) simultaneously. The 12/13-bit resolution supports 70+ dB SNR, adequate for general-purpose instrumentation, and the QFN-EP 9x9 mm footprint fits inside compact handheld enclosures. Internal reference trimming simplifies factory calibration by removing an external reference adjustment loop.
Recommended
Medical Imaging Front Ends (Ultrasound)
Ultrasound beamforming arrays require many simultaneous sampled channels at tens of MHz, and the CDK2307BILP64's dual 40 MSPS pipelined ADC is well-suited to per-channel or per-pair analog front-end digitization. The CMOS output bus streams cleanly into FPGA-based beamformer pipelines without level translation. The exposed-pad QFN-EP helps dissipate the moderate continuous-conversion heat across dense probe-handle PCBs, while digital error correction maintains the linearity needed for accurate echo reconstruction.
Recommended
Industrial Process Control Data Acquisition
Multi-channel PLC and industrial DAQ cards digitizing sensor signals at moderate rates use the CDK2307BILP64 to capture two channels per IC, reducing component count and PCB area versus discrete single-channel ADCs. The internal reference eliminates drift tuning steps during factory calibration, and the pipelined architecture guarantees consistent sample timing across channels. The CMOS parallel interface simplifies connection to industrial microcontrollers and FPGAs in factory-automation systems.
Recommended
Radar and IF Signal Processing
Doppler radar and IF-stage digitizers in defense and automotive sensors typically run at 20-80 MSPS with 12-bit resolution, which matches the CDK2307BILP64's dual-channel pipelined architecture exactly. Each channel captures I or Q independently while preserving phase coherence for FFT processing downstream. The exposed-pad QFN-EP keeps junction temperatures controlled under continuous sampling, and the CMOS parallel output supports low-latency handoff to FPGA DSP pipelines.
Recommended
Multi-Channel Embedded Vision Systems
Embedded vision systems that capture dual analog sensor streams (for example, stereo vision front ends or dual-camera front ends) use the CDK2307BILP64 to digitize both channels simultaneously, preserving temporal alignment for downstream stereo processing. The 12/13-bit resolution captures subtle luminance variations, and the QFN-EP package fits alongside the image sensor connector on compact vision boards. Internal reference trimming minimizes pixel-to-pixel brightness variation across channels.
Recommended
Recommended Products Summary
Engineering reference data for CDK2307BILP64 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | CDK2307CILP40 | ADS8401IPFBRG4 | ADS8401IPFBR |
|---|---|---|---|---|
| Brand | MaxLinear (Exar / Cadeka) | MaxLinear | Texas Instruments | Texas Instruments |
| Package | 64-pin QFN-EP (9x9 mm) | 64-pin QFN-EP - same | 48-pin TQFP PowerPAD - different footprint, NOT a true drop-in | 48-pin TQFP PowerPAD - different footprint, NOT a true drop-in |
| Channels | 2 | 2 | 1 | 1 |
| Resolution | 12 / 13-bit | 12 / 13-bit | 16-bit | 16-bit |
| Sample Rate | 40 MSPS | 40 MSPS | 1 MSPS | 1 MSPS |
| Architecture | Pipelined with digital error correction | Pipelined | SAR | SAR |
| Output Interface | CMOS Parallel | CMOS Parallel | Parallel | Parallel |
| Pin Count | 64 | 64 | 48 | 48 |
Key Differentiators
- Dual-channel integration in a single QFN-EP (vs ADS8401IPFBRG4)
- Pipelined architecture for sustained 40 MSPS throughput (vs ADS8401IPFBRG4)
- Same-family drop-in compatibility (vs CDK2307CILP40)
Design Notes
The 64-pin QFN-EP exposed pad must be soldered to a continuous ground copper pour with multiple thermal vias to a ground plane on the inner PCB layer. This provides both a low-impedance analog/digital ground reference and a low theta-JB thermal path. Without the exposed-pad solder connection, the part can overheat at continuous 40 MSPS dual-channel operation. Keep analog and digital ground returns separated until they join at the exposed pad to minimize digital switching noise coupling into the analog inputs.
Route the CMOS parallel digital outputs with matched-length traces to the FPGA or ASIC to minimize clock-to-data skew. Place a small series resistor (22-33 ohm) at each CMOS output to dampen transmission-line reflections when driving traces longer than about 25 mm. Keep digital output traces away from the analog input traces and the reference decoupling node; the parallel CMOS bus is a strong source of digital switching noise.
Estimated: based on a typical dual 40 MSPS pipelined ADC current of ~50 mA on AVDD and ~30 mA on DVDD, total supply power is approximately 240 mW with 3.3 V supplies. Provide local 0.1 uF ceramic decoupling capacitors placed within 3 mm of each AVDD and DVDD pin, plus a 10 uF bulk capacitor near the device. Use ferrite beads between analog and digital 3.3 V rails to prevent digital supply noise from corrupting the analog supply rail.
Compliance Information
RoHS / REACH / lead-free status not explicitly stated in the provided web data; set to 'unknown' rather than assume. Not AEC-Q100 qualified - this is a commercial/industrial-grade ADC; for automotive designs consult MaxLinear's automotive-grade ADC portfolio.
