CDK8307BILP64 - Octal 12/13-bit 40MSPS LVDS ADC | MaxLinear
MPN: CDK8307BILP64 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $36.5 | $36.50 |
| 10 | $32.85 | $328.50 |
| 100 | $28.1 | $2,810.00 |
| 500 | $24.75 | $12,375.00 |
| 1,000 | $21.4 | $21,400.00 |
CDK8307BILP64 Overview
An analog-to-digital converter is an integrated circuit that samples continuous analog voltage levels and converts them into discrete digital codes for downstream processing. The CDK8307 belongs to the pipelined multi-channel ADC family (a successor to successive-approximation and flash architectures) and is widely used in medical imaging, sonar, industrial inspection, and multi-channel data acquisition systems where several signals must be captured simultaneously from a common clock edge.
Key features include a programmable 12- or 13-bit resolution mode, an integrated low-jitter PLL, an internal bandgap reference, per-channel power-down control, and LVDS-compatible serial outputs that minimize EMI in dense multi-channel layouts. The PLL generates the internal ADC clock from a low-frequency reference, simplifying board design when the host FPGA or ASIC cannot supply a clean high-frequency sampling clock. The serial LVDS interface transmits the eight conversion streams over a reduced pin count compared with parallel CMOS ADCs.
The CDK8307 architecture is built on a proprietary multi-stage pipeline that re-uses a sample-and-hold section across cycles, achieving the ultra-low power profile that distinguishes this part. Per-channel power-down allows unused channels to be gated when system requirements change, and the integrated reference reduces external BOM. The PLL-supported clock multiplication delivers deterministic sample timing across all eight channels simultaneously.
Typical applications include portable and cart-based ultrasound beamforming, multi-channel sonar arrays, industrial flaw detection, and multi-axis vibration monitoring systems. The 280 mW total dissipation makes the CDK8307 particularly attractive for hand-held or battery-powered imaging systems where thermal budget is constrained. The combination of octal integration, LVDS outputs, and ultra-low power is the reason this part appears in mainstream ultrasound front-end designs.
When designing with this device, allocate a continuous ground plane beneath the QFN thermal pad and stitch vias to inner ground layers to keep digital return currents away from the analog inputs. Drive each analog input through an AC-coupling network followed by a wide-bandwidth differential driver; the LVDS outputs require a 100-ohm termination at the receiver side. Always enter the recommended power-up sequence documented in the manufacturer datasheet before applying the analog inputs.
This page synthesizes real-time distributor pricing, drop-in alternatives verified against the 64-pin QFN footprint, and practical multi-channel ADC design notes not aggregated elsewhere in a single view.
Drop-in alternatives for CDK8307BILP64 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with CDK8307BILP64 (same form factor and footprint) — differing in Package, Number of Channels, Resolution, Input Type, Reference.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
CDK8307CILP64
✅ Drop-In✓ In Stock
$11.95 / Unit
View Datasheet →AD9268XCPZ-125
✅ Drop-In✓ In Stock
$30.95 / Unit
View Datasheet →AD9629XCPZ-40
✅ Drop-In✓ In Stock
$7.45 / Unit
View Datasheet →ADS6425IRGCR
✅ Drop-In✓ In Stock
$23.1 / Unit
View Datasheet →ADS6424IRGC25
✅ Drop-In✓ In Stock
$31.2 / Unit
View Datasheet →CDK8307BILP64 Maximum Ratings & Electrical Characteristics
| Product Type | Octal Analog-to-Digital Converter (ADC) |
| Resolution | 12-bit or 13-bit (programmable) |
| Sample Rate (per channel) | 20 / 40 / 50 / 65 MSPS |
| Number of Channels | 8 |
| Total Power Dissipation | 280 mW |
| Data Output Interface | Serial LVDS |
| Input Type | Differential analog inputs (one per channel) |
| Reference | Internal (integrated bandgap reference) |
| Clock Architecture | External reference clock with integrated PLL (x12 or x14 multiplication) |
| Control Interface | Serial control interface |
| Package | 64-pin QFN (LP suffix) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
CDK8307BILP64 Pin Configuration
| Pin 1 | AINP0 — Differential analog input positive, channel 0 |
| Pin 2 | AINN0 — Differential analog input negative, channel 0 |
| Pin 3 | AINP1 — Differential analog input positive, channel 1 |
| Pin 4 | AINN1 — Differential analog input negative, channel 1 |
| Pin 5 | AINP2 — Differential analog input positive, channel 2 |
| Pin 6 | AINN2 — Differential analog input negative, channel 2 |
| Pin 7 | AINP3 — Differential analog input positive, channel 3 |
| Pin 8 | AINN3 — Differential analog input negative, channel 3 |
| Pin 9 | AINP4 — Differential analog input positive, channel 4 |
| Pin 10 | AINN4 — Differential analog input negative, channel 4 |
| Pin 11 | AINP5 — Differential analog input positive, channel 5 |
| Pin 12 | AINN5 — Differential analog input negative, channel 5 |
| Pin 13 | AINP6 — Differential analog input positive, channel 6 |
| Pin 14 | AINN6 — Differential analog input negative, channel 6 |
| Pin 15 | AINP7 — Differential analog input positive, channel 7 |
| Pin 16 | AINN7 — Differential analog input negative, channel 7 |
| Pin 17 | VCM — Common-mode voltage bypass |
| Pin 18 | REFP — Internal reference positive decoupling |
| Pin 19 | REFN — Internal reference negative decoupling |
| Pin 20 | VDDA — Analog supply |
| Pin 21 | VSSA — Analog ground |
| Pin 22 | CLK+ — Differential reference clock positive input |
| Pin 23 | CLK- — Differential reference clock negative input |
| Pin 24 | PDOWN — Per-channel power-down control |
| Pin 25 | RESETB — Reset, active low |
| Pin 26 | SCLK — Serial control interface clock |
| Pin 27 | SDIN — Serial control interface data input |
| Pin 28 | SDOUT — Serial control interface data output |
| Pin 29 | SENB — Serial control interface enable, active low |
| Pin 30 | RESERVED — Reserved - tie to ground per datasheet |
| Pin 31 | VDD_DIG — Digital supply |
| Pin 32 | VSS_DIG — Digital ground |
| Pin 33 | D0P — LVDS data output lane 0 positive |
| Pin 34 | D0N — LVDS data output lane 0 negative |
| Pin 35 | D1P — LVDS data output lane 1 positive |
| Pin 36 | D1N — LVDS data output lane 1 negative |
| Pin 37 | D2P — LVDS data output lane 2 positive |
| Pin 38 | D2N — LVDS data output lane 2 negative |
| Pin 39 | D3P — LVDS data output lane 3 positive |
| Pin 40 | D3N — LVDS data output lane 3 negative |
| Pin 41 | D4P — LVDS data output lane 4 positive |
| Pin 42 | D4N — LVDS data output lane 4 negative |
| Pin 43 | D5P — LVDS data output lane 5 positive |
| Pin 44 | D5N — LVDS data output lane 5 negative |
| Pin 45 | D6P — LVDS data output lane 6 positive |
| Pin 46 | D6N — LVDS data output lane 6 negative |
| Pin 47 | D7P — LVDS data output lane 7 positive |
| Pin 48 | D7N — LVDS data output lane 7 negative |
| Pin 49 | D8P — LVDS data output lane 8 positive (frame/clock) |
| Pin 50 | D8N — LVDS data output lane 8 negative (frame/clock) |
| Pin 51 | D9P — LVDS data output lane 9 positive (bit clock) |
| Pin 52 | D9N — LVDS data output lane 9 negative (bit clock) |
| Pin 53 | VDD_LVDS — LVDS output supply |
| Pin 54 | VSS_LVDS — LVDS output ground |
| Pin 55 | RESERVED — Reserved - tie to ground per datasheet |
| Pin 56 | RESERVED — Reserved - tie to ground per datasheet |
| Pin 57 | RESERVED — Reserved - tie to ground per datasheet |
| Pin 58 | RESERVED — Reserved - tie to ground per datasheet |
| Pin 59 | RESERVED — Reserved - tie to ground per datasheet |
| Pin 60 | RESERVED — Reserved - tie to ground per datasheet |
| Pin 61 | RESERVED — Reserved - tie to ground per datasheet |
| Pin 62 | RESERVED — Reserved - tie to ground per datasheet |
| Pin 63 | RESERVED — Reserved - tie to ground per datasheet |
| Pin 64 | RESERVED — Reserved - tie to ground per datasheet |
| Pin 65 | EPAD — Exposed thermal pad - connect to analog ground with vias |
Typical Applications
CDK8307BILP64 is suitable for 6 applications: Portable Ultrasound Beamforming Front-End, Multi-Channel Sonar Receiver Arrays, Industrial Flaw Detection and Non-Destructive Testing, Multi-Axis Vibration Monitoring Systems, Multi-Channel Data Acquisition (DAQ) Modules, Battery-Powered Portable Instrumentation.
Portable Ultrasound Beamforming Front-End
The CDK8307BILP64's octal channel integration at 280 mW total is purpose-built for portable ultrasound beamforming where each transducer element must be digitized synchronously. The 64-pin QFN integrates eight 12/13-bit ADCs along with a PLL that multiplies a low-frequency reference by 12 or 14, allowing the system ASIC to drive a slow reference clock and still achieve deterministic 40 to 65 MSPS sampling. The serial LVDS outputs minimize routing density between the probe head and the back-end FPGA, which is critical for hand-held and cart-based probes where the cable bundle is small. A typical chain pairs the CDK8307 with an LVDS deserializer such as the SCAN921025 plus an FPGA running delay-and-sum beamforming.
Recommended
Multi-Channel Sonar Receiver Arrays
Sonar arrays require time-synchronized sampling across dozens of hydrophones, and the CDK8307BILP64 delivers eight synchronized ADC channels per chip at 65 MSPS, allowing cascaded arrays to scale to 64+ channels. The low 280 mW dissipation is critical for towfish and autonomous underwater vehicle (AUV) systems where heat must be rejected to the surrounding water through a sealed enclosure. The LVDS outputs are tolerant of long cable runs back to the surface vessel, and the integrated PLL simplifies clock distribution on the wet-end board. Designers typically follow the CDK8307 with an FPGA-based digital beamformer that computes the bearing-time display in real time.
Recommended
Industrial Flaw Detection and Non-Destructive Testing
Industrial phased-array ultrasonic testing (PAUT) probes need to digitize 16 to 128 transducer elements concurrently while the probe is scanned along a weld or composite panel. The CDK8307BILP64 supports this scenario with eight 12/13-bit ADCs sharing one LVDS bus, with four to sixteen CDK8307 devices typically daisy-chained on the probe handle. At 280 mW total, the ADC array can be sealed in a compact housing without active cooling, and the integrated PLL keeps the local oscillator simple. A reference design combines the CDK8307 with an FPGA-anchored total-focusing-method (TFM) processor for real-time imaging.
Recommended
Multi-Axis Vibration Monitoring Systems
Condition-monitoring systems on industrial machinery use ICP/IEPE accelerometers on multiple bearings, shafts and gearboxes, and each axis must be sampled at 40 kHz or higher to capture bearing-fault signatures above 10 kHz. The CDK8307BILP64 provides eight simultaneously sampled channels with 12-bit resolution sufficient for envelope analysis, and the 65 MSPS oversampling ceiling provides plenty of headroom for anti-alias filtering. The LVDS interface transports data back to a controller over shielded twisted pair, ideal for noisy industrial environments. A common companion is an op-amp buffer front-end and an ARM Cortex-M4 host for FFT processing.
Recommended
Multi-Channel Data Acquisition (DAQ) Modules
DAQ modules for laboratory and test instrumentation benefit from the CDK8307BILP64's eight channels per chip, allowing a single PXI card to host 32 or 64 simultaneous analog inputs. The 12/13-bit resolution and 65 MSPS capability suits mid-tier digitizers covering audio, ultrasonic and general-purpose sensor capture. The serial LVDS outputs keep the backplane free of parallel CMOS buses and let the FPGA on the card process data at high throughput. A typical front-end pairs the CDK8307 with an input protection network and a software-selectable differential amplifier.
Recommended
Battery-Powered Portable Instrumentation
The CDK8307BILP64's 280 mW total dissipation across eight channels translates to 35 mW per channel, an order of magnitude below older CMOS multi-channel ADCs and ideal for battery-powered portable instruments. Field data loggers, handheld spectrum analyzers and portable medical spot-check devices all benefit from this efficiency. The integrated reference and PLL reduce external BOM and quiescent draw, while per-channel power-down allows unused channels to be turned off to extend runtime. A typical reference design pairs the CDK8307 with a LiFePO4 battery, a low-dropout regulator and a low-power FPGA host.
Recommended
Recommended Products Summary
Engineering reference data for CDK8307BILP64 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | CDK8307CILP64 | AD9268XCPZ-125 | AD9629XCPZ-40 | ADS6425IRGCR | ADS6424IRGC25 |
|---|---|---|---|---|---|---|
| Brand | MaxLinear | MaxLinear | Analog Devices | Analog Devices | Texas Instruments | Texas Instruments |
| Package | QFN-64 (LP) | QFN-64 - same | LFCSP/QFN-64 - same | LFCSP/QFN-64 - same | QFN-64 (RGCT) - same | QFN-64 (RGC) - same |
| Number of Channels | 8 | 8 | 8 | 2 | 4 (stacked 8-channel equivalent) | 4 |
| Resolution | 12/13-bit programmable | 12/13-bit | 14-bit | 12-bit | 12-bit | 12-bit |
| Max Sample Rate (per channel) | 65 MSPS | 65 MSPS | 125 MSPS (+92%) | 40 MSPS | 125 MSPS | 40 MSPS |
| Output Interface | Serial LVDS | Serial LVDS | LVDS | LVDS | LVDS | LVDS |
| Integrated PLL | Yes (x12 or x14) | Yes | No (external clock required) | No (external clock required) | No (external clock required) | No (external clock required) |
| Internal Reference | Yes (bandgap) | Yes | Internal | Internal | Internal | Internal |
Key Differentiators
- Octal channel integration with 280 mW total dissipation (vs AD9268XCPZ-125)
- Integrated PLL eliminates external high-frequency clock (vs AD9629XCPZ-40)
- 12/13-bit resolution switching in the same chip (vs ADS6425IRGCR)
Design Notes
Estimated: at 280 mW dissipation across the 64-pin QFN package with exposed thermal pad, layout should stitch at least 16 thermal vias directly under the EPAD to a continuous inner ground plane. Without this thermal relief, the junction temperature can rise 30 to 40 C above ambient in enclosed portable enclosures, which may degrade ADC linearity at the highest sample rates.
Route the eight analog inputs as length-matched 100-ohm differential pairs from the input connector or amplifier to each AINP/N pair, keeping the pairs well isolated from the LVDS output pairs. Place the analog input common-mode bypass (VCM) capacitor within 5 mm of the VCM pin. The CLK+/CLK- differential pair requires the same 100-ohm impedance and must be shielded from noisy digital traces to maintain the PLL jitter budget.
Do not apply analog input signals before completing the recommended power-up sequence documented in the manufacturer datasheet. Driving the analog pins before the internal reference and PLL stabilize can latch the ADC into a non-recoverable state that requires a full power cycle. Also, when switching between 12-bit and 13-bit modes, re-issue the serial control interface command with the SENB logic-level sequencing described in the datasheet.
Compliance Information
RoHS status confirmed in distributor listing. Reach, halogen-free, and conflict-mineral declarations not present in verified web data and remain unknown.
