DP83848IVV - 10/100 Ethernet PHY Transceiver | Texas Instruments
MPN: DP83848IVV ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.95 | $8.95 |
| 10 | $8.05 | $80.50 |
| 100 | $7.15 | $715.00 |
| 500 | $6.42 | $3,210.00 |
| 1,000 | $5.73 | $5,730.00 |
DP83848IVV Overview
An Ethernet PHY (Physical Layer Device) is a transceiver IC that sits between a MAC controller and the copper media (twisted pair), handling analog line driving/receiving, clock recovery, link monitoring, and 10BASE-T/100BASE-TX encoding/decoding. PHYTERs are a category of Ethernet PHYs that emphasize robust industrial-grade operation, sitting within the broader Ethernet controller hierarchy: PHY -> transceiver -> network interface device -> communication IC -> semiconductor.
Key features of the DP83848IVV include integrated 100BASE-TX/FX physical coding sublayer (PCS) and physical media attachment (PMA), 3.3V single-rail operation with 2.5V internal LDO, Auto-MDIX crossover detection, Energy Detect Plus power-down modes, and 4 kV ESD tolerance on the MDI pins. The device also features low-latency (sub-100ns) MII throughput, hardware pause-frame support for flow control, and an IEEE 1149.1 JTAG boundary-scan port for board test. The 48-LQFP package provides a thermally efficient surface-mount footprint with 31.4 C/W typical junction-to-ambient resistance.
Architecture-wise, the DP83848IVV combines a DSP-based receive path with adaptive equalization to recover signals over >150m of CAT-5 cable, a 125 MHz PLL for 100BASE-TX clocking, and a 25 MHz crystal interface or external clock input. Internal voltage regulation simplifies power tree implementation by accepting a single 3.3V supply.
The DP83848IVV is designed for industrial Ethernet nodes, factory automation controllers, motor drives with EtherCAT/PROFINET bridges, building-automation gateways, IP-based surveillance cameras, and any embedded MCU/MPU with MII/RMII needing 10/100 connectivity. Its -40C to +85C industrial temperature grade supports deployment in harsh environments.
When designing with the DP83848IVV, follow TI's reference layout for the magnetics and 49.9 ohm 1% termination resistors as specified in the datasheet application section. Use a 25 MHz crystal or feed a clean external CMOS clock; keep the MDI traces length-matched within 50 mils and 100-ohm differential-impedance controlled for best EMI margin.
Drop-in alternatives for DP83848IVV — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DP83848IVV (same form factor and footprint) — differing in Auto-MDIX, Auto-Negotiation, MAC Interface, Operating Temperature, Package.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DP83848CVV/NOPB
✅ Drop-In📋 Reference alternative (not in catalog)
DP83848EVV/NOPB
✅ Drop-In📋 Reference alternative (not in catalog)
DP83848IVV/NOPB
✅ Drop-In📋 Reference alternative (not in catalog)
DP83848IVV Specifications
| Product Type | Ethernet PHY Transceiver |
| Data Rate | 10/100 Mbps |
| Standards | IEEE 802.3u, IEEE 802.3 |
| Number of Ports | 1 |
| MAC Interface | MII / RMII |
| Supply Voltage | 3.3 V |
| Operating Temperature | -40C to +85C (Industrial) |
| Package | 48-LQFP (7x7 mm) |
| Auto-MDIX | Yes |
| Auto-Negotiation | Yes |
| Power-Down Modes | Energy Detect Plus |
| JTAG Support | IEEE 1149.1 |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (NOPB suffix) |
DP83848IVV Pin Configuration
| Pin 1 | TXD0 — Transmit Data bit 0 (MII) |
| Pin 2 | TXD1 — Transmit Data bit 1 (MII) |
| Pin 3 | TXD2 — Transmit Data bit 2 (MII) |
| Pin 4 | TXD3 — Transmit Data bit 3 (MII) |
| Pin 5 | TX_EN — Transmit Enable (MII) |
| Pin 6 | TX_CLK — Transmit Clock 25 MHz output (MII) |
| Pin 7 | TX_ER — Transmit Coding Error (MII) |
| Pin 8 | COL — Collision Detect (MII) |
| Pin 9 | RXD0 — Receive Data bit 0 (MII) |
| Pin 10 | RXD1 — Receive Data bit 1 (MII) |
| Pin 11 | RXD2 — Receive Data bit 2 (MII) |
| Pin 12 | RXD3 — Receive Data bit 3 (MII) |
| Pin 13 | RX_DV — Receive Data Valid (MII) |
| Pin 14 | RX_CLK — Receive Clock 25 MHz output (MII) |
| Pin 15 | RX_ER — Receive Error (MII) |
| Pin 16 | CRS — Carrier Sense (MII) |
| Pin 17 | MDC — Management Data Clock |
| Pin 18 | MDIO — Management Data I/O |
| Pin 19 | RESET_N — Hardware Reset (active-low) |
| Pin 20 | X1 — 25 MHz Crystal In |
| Pin 21 | X2 — 25 MHz Crystal Out |
| Pin 22 | LED0/PHYAD0 — LED 0 / PHY Address strap |
| Pin 23 | LED1/PHYAD1 — LED 1 / PHY Address strap |
| Pin 24 | LED2/PHYAD2 — LED 2 / PHY Address strap |
| Pin 25 | LED3/AN0 — LED 3 / Auto-Neg strap |
| Pin 26 | LED4/AN1 — LED 4 / Auto-Neg strap |
| Pin 27 | NC — Not connected (per datasheet) |
| Pin 28 | TD+ — Differential transmit positive |
| Pin 29 | TD- — Differential transmit negative |
| Pin 30 | NC — Not connected (per datasheet) |
| Pin 31 | RD+ — Differential receive positive |
| Pin 32 | RD- — Differential receive negative |
| Pin 33 | NC — Not connected (per datasheet) |
| Pin 34 | GND — Ground (substrate) |
| Pin 35 | AVDD33 — Analog 3.3V supply |
| Pin 36 | AGND — Analog ground |
| Pin 37 | AVDD25 — Analog 2.5V internal LDO output (bypass cap) |
| Pin 38 | NC — Not connected (per datasheet) |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | DVDD33 — Digital 3.3V supply |
| Pin 41 | DGND — Digital ground |
| Pin 42 | TDI — JTAG Test Data In |
| Pin 43 | TDO — JTAG Test Data Out |
| Pin 44 | TMS — JTAG Test Mode Select |
| Pin 45 | TCK — JTAG Test Clock |
| Pin 46 | TRST_N — JTAG Test Reset (active-low) |
| Pin 47 | RBIN — Reduced MII mode select strap |
| Pin 48 | IOVDD33 — I/O 3.3V supply (separate pin for noise isolation) |
Typical Applications
DP83848IVV is suitable for 6 applications: Industrial Ethernet Nodes, Motor Drives with EtherCAT/PROFINET Bridges, IP Surveillance Cameras, Building Automation Gateways, Embedded Routers / IoT Gateways, Test & Measurement Equipment.
Industrial Ethernet Nodes
The DP83848IVV's -40C to +85C industrial temperature grade and 48-LQFP compact footprint make it ideal for factory-floor PLCs and remote I/O blocks requiring 10/100 Ethernet connectivity. Its integrated Auto-MDIX eliminates crossover-cable mistakes by technicians in field installations. Placed between an MCU/MAC and the RJ45 magnetics, it provides 100 m CAT-5 reach with on-die adaptive equalization that recovers signals cleanly in electrically noisy cabinet environments. The 3.3V single-rail operation simplifies power-tree design on 24V-input industrial boards.
Recommended
Motor Drives with EtherCAT/PROFINET Bridges
Industrial servo drives and variable-frequency motor drives need 10/100 Ethernet to host PLCs over EtherCAT, PROFINET, or Ethernet/IP. The DP83848IVV supports these protocols via the MII interface to protocol-specific MAC ASICs from Beckhoff, Siemens, or HMS. Its industrial temperature rating ensures stable operation in sealed drive enclosures reaching 70C+. The 48-LQFP-7x7 fits within typical 50x80mm motor control boards, leaving room for IGBT/MOSFET power components nearby.
Recommended
IP Surveillance Cameras
Outdoor PoE-powered IP cameras need a robust 10/100 PHY operating in -40C ambient temperature extremes. The DP83848IVV's industrial temperature grade and Auto-MDIX simplify installation, while its energy-detect power-down mode enables <100 mW standby consumption. Placed between the image sensor SoC's MAC and the RJ45 jack, it streams 1080p30 H.264/265 video at 100 Mb/s with sub-100-ns MII latency. The 48-LQFP package provides thermal headroom for sealed IP67 housings without additional heatsinking.
Recommended
Building Automation Gateways
BACnet/IP, KNXnet/IP, and Modbus-TCP building-automation gateways require reliable 10/100 Ethernet in ceiling-mounted enclosures. The DP83848IVV's Auto-MDIX eliminates wiring mistakes in field installations by contractors unfamiliar with crossover cables. Its 3.3V single-supply operation simplifies power design on shared 24V building rails, and the 48-LQFP package with 7x7 mm footprint fits in compact DIN-rail gateway housings. JTAG support enables boundary-scan verification during board bring-up for reliable multi-year deployments.
Recommended
Embedded Routers / IoT Gateways
Edge routers and IoT gateways with 10/100 WAN/LAN ports benefit from the DP83848IVV's low-latency MII throughput and hardware pause-frame flow control. The device pairs naturally with embedded Linux MCUs (i.MX RT, AM335x) for OpenWrt-based routers. Its energy-detect power-down reduces idle consumption below 50 mW when the cable is unplugged, critical for energy-star IoT products. The integrated 2.5V LDO saves the cost of an external regulator on space-constrained gateway boards.
Recommended
Test & Measurement Equipment
Lab instruments such as oscilloscopes, spectrum analyzers, and protocol analyzers need reliable LXI-compliant 10/100 Ethernet connectivity for SCPI remote control. The DP83848IVV's IEEE 1149.1 JTAG interface simplifies board boundary-scan testing during manufacturing test, and its hardware pause-frame support enables lossless capture streaming. Placed between an FPGA MAC and the rear-panel RJ45 jack, it provides 100 Mb/s throughput sufficient for waveform upload in <2 seconds for typical 100 MB acquisitions.
Recommended
Recommended Products Summary
Engineering reference data for DP83848IVV — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DP83848CVV/NOPB | DP83848EVV/NOPB | DP83848IVV/NOPB |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-LQFP (7x7 mm) | 48-LQFP (7x7 mm) - same | 48-LQFP (7x7 mm) - same | 48-LQFP (7x7 mm) - same |
| Data Rate | 10/100 Mbps | 10/100 Mbps | 10/100 Mbps | 10/100 Mbps |
| Operating Temperature | -40C to +85C (Industrial) | 0C to +70C (Commercial) | -40C to +105C (Extended) | -40C to +85C (Industrial) |
| MAC Interface | MII / RMII | MII / RMII | MII / RMII | MII / RMII |
| Supply Voltage | 3.3V | 3.3V | 3.3V | 3.3V |
| Auto-MDIX | Yes | Yes | Yes | Yes |
| RoHS Compliant | With /NOPB suffix | Yes | Yes | Yes |
Key Differentiators
- Wider industrial temperature grade (vs DP83848CVV/NOPB)
- Lower cost vs extended-temperature E variant (vs DP83848EVV/NOPB)
- Most widely stocked DP83848 grade (vs DP83848IVV/NOPB)
Design Notes
Follow TI's reference layout for the DP83848IVV: place the 49.9 ohm 1% termination resistors within 5 mm of the TD+/TD- and RD+/RD- pins. The differential MDI traces must be 100-ohm differential impedance and length-matched within 50 mils for IEEE 802.3u compliance. Keep analog and digital ground planes separated and join only at the EPAD ground pins. Use a 4-layer stack-up with a continuous ground plane beneath the device for best EMI performance.
Bypass each supply pin (AVDD33, DVDD33, IOVDD33) with a 0.1 uF X7R ceramic capacitor within 2 mm of the pin. Add a 10 uF bulk tantalum or ceramic at the device's main supply input. The internal 2.5V LDO requires a 0.1 uF + 10 uF bypass cap on the AVDD25 pin for PLL clean operation. Use a ferrite bead between digital and analog 3.3V rails to isolate switching noise.
Do not omit the 25 MHz crystal or external CMOS clock on X1/X2 - the PHYTER has no internal oscillator. Strapping pins (PHYAD, RBIN, AN) are read only at hardware reset; do not drive them with active signals during reset. Auto-MDIX requires Auto-Negotiation to be enabled. For fiber-only FX applications, choose the DP83848VF variant instead - the IVV supports FX only when the MDI pins are properly reconfigured via the FXD strap.
Compliance Information
RoHS/REACH compliant only with /NOPB suffix. Standard DP83848IVV (without NOPB) is non-RoHS. Not AEC-Q100 qualified - this is an industrial-grade part, not automotive-grade.
