DS90C383MTDX - 65MHz Programmable LVDS Transmitter | TI
MPN: DS90C383MTDX ✓ ActiveDS90C383MTDX Overview
A flat-panel display link, or FPD-Link, is a high-speed serial interface that transfers parallel pixel data and timing information between a graphics controller and a display. LVDS, or Low Voltage Differential Signaling, uses low-amplitude differential signals to support reliable point-to-point data transfer while limiting voltage noise and electromagnetic interference. The DS90C383MTDX belongs to the broader interface IC and display-interface hierarchy.
The transmitter includes programmable rising-edge or falling-edge data strobe operation, allowing it to work with different graphics-controller timing. A rising-edge implementation can interoperate with the falling-edge DS90CF384 receiver without translation logic. The dedicated configuration pin provides a convenient way to align the transmitter's output strobe with the receiving system and simplifies adaptation between source and display timing conventions.
The DS90C383 family pairs the DS90C383 transmitter with the DS90CF384 receiver for a complete LVDS display link. The transmit path preserves parallel pixel information as four differential data channels while adding a separate differential clock channel. This organization supports compact interconnects between display-controller boards and large-panel assemblies while reducing the number of single-ended signals routed over cables or board-to-board interfaces.
Typical uses include digital flat-panel monitor links, industrial display controllers, automotive display systems, point-of-sale terminals, and other LVDS-equipped visual systems. The 24-bit color payload and 65 MHz operating capability suit parallel RGB pixel streams that must be serialized before reaching a panel interface. System designers still need to verify source timing, receiver polarity, connector routing, and cable-length limitations against the device electrical requirements.
For layout, place the transmitter close to the LVDS output connector and route the five differential links as tightly coupled pairs on a continuous reference plane. Keep LVDS traces away from switching nodes and maintain a solid ground reference beneath the links. The graphics-controller interface also requires careful clock and data timing review because programmable strobe polarity changes when data is captured relative to the transmitted clock.
This page combines the manufacturer's interface description, 227 Mbps and 65 MHz operating information, package details, pin-compatible alternatives, and practical link-design guidance. It also distinguishes the transmitter from the related DS90CF384 receiver and identifies which parameters require confirmation before substitution or production release.
Drop-in alternatives for DS90C383MTDX — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DS90C383MTDX (same form factor and footprint) — differing in Product Type, Data Width, Pin Count.
DS90C383MTD
✅ Drop-InContact for price
View Datasheet →DS90C383SLC
✅ Drop-InContact for price
View Datasheet →DS90CF383MTD
✅ Drop-In📋 Reference alternative (not in catalog)
DS90CF386MTD
✅ Drop-In📋 Reference alternative (not in catalog)
DS90CR286AMTD
✅ Drop-In📋 Reference alternative (not in catalog)
DS90C383MTDX Specifications
| Product Type | Programmable LVDS flat-panel display transmitter |
| Supply Voltage | 3.3 V |
| Maximum Clock Frequency | 65 MHz |
| Supported Data Rate | 227 Mbps |
| Input Data Width | 28 bits |
| Pixel Data Width | 24 bits |
| LVDS Data Streams | 4 differential streams |
| LVDS Clock Links | 1 differential phase-locked transmit clock link |
| Input Logic | LVCMOS/LVTTL |
| Output Logic | LVDS |
| Programmable Data Strobe | Rising edge or falling edge |
| Package | 56-pin TSSOP |
| Pin Count | 56 pins |
| Mounting Type | Surface mount |
DS90C383MTDX 56-pin tssop Pin Configuration Guide
Pin configuration for DS90C383MTDX (56-pin tssop package). Pin numbering, functions, and connection diagrams are defined in the manufacturer datasheet. Refer to it for the exact footprint and soldering guidelines.
No detailed pinout data available for DS90C383MTDX.
Refer to the datasheet for full pin configuration.
Typical Applications
DS90C383MTDX is suitable for 6 applications: Digital Flat-Panel Monitor Links, Industrial Panel Interfaces, Automotive Display Controllers, Point-of-Sale Terminal Displays, Video Test and Measurement Equipment, Compact Embedded Display Systems.
Digital Flat-Panel Monitor Links
The DS90C383MTDX is appropriate for a digital monitor link that carries 24-bit color data from a graphics controller to a panel receiver. Its 28-bit parallel input is serialized into four LVDS data links plus one clock link, supporting a 227 Mbps data rate and a maximum clock frequency of 65 MHz. Using differential links reduces the number of high-speed single-ended traces on the board and across the panel interconnect. The design should match receiver edge timing and verify connector and cable requirements against the TI application information.
Recommended
Industrial Panel Interfaces
The DS90C383MTDX can serialize parallel pixel data for industrial panels that use a 3.3 V LVDS input. Its 24-bit payload, four differential data outputs, separate phase-locked clock link, and programmable strobe polarity provide a practical interface between controller logic and remote display electronics. Differential signaling is particularly useful where cable routing or ground offsets could compromise a multi-bit single-ended interface. Engineers should still assess industrial temperature requirements, grounding, ESD protection, and panel connector implementation before production release.
Recommended
Automotive Display Controllers
The DS90C383MTDX can serve as the transmitter side of a 3.3 V LVDS display connection in an automotive controller, provided the exact ordering code satisfies the vehicle program's temperature, quality, and qualification requirements. Its four data links and separate clock link accommodate a 24-bit pixel stream at up to 227 Mbps while preserving a low-amplitude differential interface. Vehicle implementations also require careful review of ground offsets, cable length, connector loss, transient protection, and electromagnetic compatibility.
Recommended
Point-of-Sale Terminal Displays
A point-of-sale terminal can use the DS90C383MTDX to bridge parallel graphics-controller outputs to a compact remote LVDS display. The 28-bit input accepts the 24-bit pixel payload plus four associated data bits, while the 65 MHz clock capability supports the intended display timing. Differential outputs reduce signal-integrity risk across internal cables and connectors compared with a wide parallel bus. The implementation should verify the terminal's native refresh timing, LCD input compatibility, cable length, and available panel input timing before selecting the strobe edge.
Recommended
Video Test and Measurement Equipment
The DS90C383MTDX is useful in test equipment that must generate or adapt standardized LVDS display signals for a panel, display fixture, or video-processing module. Its programmable rising- or falling-edge data strobe allows source timing to be aligned with different receiver conventions, while the separate transmit-clock link simplifies synchronization. A bench fixture can compare receiver polarity, cable integrity, and data timing under controlled conditions. Use short, controlled interconnect paths and verify that every attached receiver has the required FPD-Link configuration.
Recommended
Compact Embedded Display Systems
Embedded processors and programmable logic can feed the DS90C383MTDX when their native interface is parallel but the display requires LVDS. The transmitter consolidates the pixel and associated data into four differential channels and adds a dedicated phase-locked clock channel, reducing connector pin demand and improving noise immunity. This arrangement is suitable for compact industrial, medical, and communications equipment with remote panel connections. The source design must still establish deterministic timing, provide compatible I/O voltage levels, and account for LVDS receiver configuration and cable loss.
Recommended
Recommended Products Summary
Engineering reference data for DS90C383MTDX — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DS90C383MTD | DS90C383 | DS90CF383MTD | DS90CF386MTD | DS90CR286AMTD |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 56-TSSOP | 56-TSSOP | 56-TSSOP | 56-TSSOP | 56-TSSOP | 56-TSSOP |
| Device Class | 24-bit FPD-Link LVDS transmitter | 24-bit FPD-Link transmitter | 24-bit FPD-Link transmitter | Related FPD-Link device | Related FPD-Link device | Related interface device |
Key Differentiators
- Identifies itself as the transmitter in the DS90C383 FPD-Link family (vs DS90CF383MTD)
- Supports programmable rising-edge or falling-edge transmission (vs DS90C383MTD)
- Provides a 65 MHz clock with a 227 Mbps link rate (vs DS90CF386MTD)
- Matches the established 56-pin TSSOP display-link footprint (vs DS90CR286AMTD)
Design Notes
Route each LVDS signal as a tightly coupled differential pair over a continuous ground reference. Keep the four data links and the separate transmit-clock link away from switching nodes and noisy power-regulator return paths. Place the transmitter close to the output connector, minimize stubs, and maintain the same general geometry for the paired traces to reduce skew and radiated emissions.
Verify source and receiver edge relationships before enabling the link. The DS90C383 can transmit with rising-edge or falling-edge strobes, and a rising-edge transmitter interoperates with the falling-edge DS90CF384 receiver. Use the timing diagrams to confirm which data is valid at the receiver, and include cable and connector propagation delay when the displayed image depends on exact pixel-clock alignment.
Do not substitute a related 56-pin display-link device based on package appearance alone. Confirm that the alternative is a transmitter, matches the 65 MHz clock and 227 Mbps data-rate requirements, supports the required 28-bit parallel input, and has compatible strobe and control-pin behavior. Review the complete pin-description table and timing requirements before releasing a cross-reference into production.
Keep the LVDS interface away from clocks, switching regulators, and high-current return paths, especially where both sides of a differential pair might cross unrelated aggressors. A continuous reference plane and short connector path generally produce a cleaner result than an uneven pair geometry. If emissions or data errors appear, inspect the return-current path and compare the edge-selection configuration before changing cable or receiver hardware.
Compliance Information
The manufacturer product page and device summary do not establish the requested compliance statuses. Confirm RoHS, REACH, AEC-Q100, lead-free, halogen-free, and conflict-minerals declarations for the exact DS90C383MTDX ordering code before procurement release.
