DS90C383SLC - 3.3V 24-Bit 65MHz LVDS Transmitter | TI
MPN: DS90C383SLC ✗ End of LifeDS90C383SLC Overview
An LVDS transmitter is a display-interface device that transmits data across a balanced differential link using low-voltage signaling. The technology hierarchy is LVDS transmitter to differential line driver, display interface IC, interface IC, and semiconductor. FPD-Link systems commonly pair such a transmitter with an LVDS receiver at the far end of a cable or PCB trace, reducing signal-integrity and common-mode-noise problems compared with single-ended parallel transmission.
The principal verified characteristics are a 3.3-V supply, programmable operation, a 24-bit parallel data interface, and a 65-MHz maximum link clock. According to the manufacturer product page, these features position the DS90C383 for flat-panel-display links where serialized differential transport is needed. Its broad parallel input bus supports multiple display pixels or source-synchronous interface signals while reducing the number of signal conductors required between the transmitter and receiver.
The DS90C383SLC uses the TI FPD-Link approach to move display information from a graphics source to a panel receiver. The differential output helps reject common-mode noise, while serialized data reduces skew exposure across many parallel conductors. Programmable transmitter configuration provides the system designer with control over the link behavior. Exact output voltage, termination, current, and timing limits require confirmation in the manufacturer datasheet because they are not included in the supplied web results.
Typical uses include small-format LCD panels, industrial human-machine-interface displays, test equipment, and other embedded systems that pair a graphics engine with an LVDS-capable display receiver. In these systems, the transmitter commonly accepts parallel pixel data and clock signals, then drives a shielded cable or controlled-length board interconnect. The receiver reconstructs the data for the panel timing controller.
The principal design consideration is that this is a high-speed differential interface, so trace geometry, connector return paths, input timing, and cable termination must follow the datasheet reference layout. Designers should also verify the exact SLC64A land pattern, supply decoupling requirements, and receiver interoperability before layout release because those details are unavailable in the supplied search snippets.
This page combines the verified 3.3-V, 24-bit, and 65-MHz device identity with current distributor pricing, manufacturer documentation links, and same-brand drop-in replacement guidance. The comparison and design guidance are intended to reduce board-rework risk while keeping every proposed replacement in the same SLC64A package family.
Drop-in alternatives for DS90C383SLC — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
DS90C385A
✅ Drop-In📋 Reference alternative (not in catalog)
DS90C383A
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DS90C385
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DS90C383SLC Specifications
| Product Type | Programmable LVDS transmitter |
| Supply Voltage | 3.3 V |
| Data Width | 24 bit |
| Maximum Clock Frequency | 65 MHz |
| Interface Standard | Flat Panel Display Link (FPD-Link) |
| Output Signaling | Low-Voltage Differential Signaling (LVDS) |
| Programmability | Programmable |
| Orderable Package Code | SLC64A |
| Package Type | 64-ball BGA |
| Package Dimensions | 8 mm x 8 mm |
| Pin Count | 64 pins |
| Mounting Type | Surface mount |
DS90C383SLC 8 mm x 8 mm Pin Configuration Guide
Pin configuration for DS90C383SLC (8 mm x 8 mm package). Pin numbering, functions, and connection diagrams are defined in the manufacturer datasheet. Refer to it for the exact footprint and soldering guidelines.
No detailed pinout data available for DS90C383SLC.
Refer to the datasheet for full pin configuration.
Typical Applications
DS90C383SLC is suitable for 6 applications: Industrial Human-Machine-Interface Displays, Small-Flat-Panel LCD Displays, Embedded Graphical Control Panels, Test and Measurement Front Panels, Point-of-Sale and Retail Terminals, Video-Capture and Imaging Workstations.
Industrial Human-Machine-Interface Displays
The DS90C383SLC fits industrial HMI designs that use a parallel graphics source and an LVDS-enabled panel. Its 24-bit data width supports display-oriented parallel traffic, while the 65-MHz maximum clock provides a defined upper operating point for serialized FPD-Link transmission. The 3.3-V supply also aligns with many embedded display-controller platforms. In implementation, the transmitter is placed between the graphics engine and panel cable, with its differential outputs routed as a controlled-impedance pair. The main qualification requirement is not raw speed but compatibility with the selected receiver, panel timing, cable length, and industrial temperature range. Because the supplied sources do not state DS90C383SLC's temperature grade or EMC classification, those items must be confirmed before deployment in a factory environment.
Recommended
Small-Flat-Panel LCD Displays
The DS90C383SLC is appropriate for small-format LCD modules whose controller supports an LVDS or FPD-Link input and requires more parallel data than a compact low-resolution interface can provide. The device accepts a 24-bit data stream and transmits it through differential signaling at up to 65 MHz, reducing the number of long parallel conductors crossing the panel boundary. This arrangement is particularly useful where EMI containment and cable weight matter. System integrators should pair it with a receiver whose lane count, pixel-clock range, and synchronization format match the panel. The transmitter itself does not generate the panel timing sequence, so upstream pixel timing and receiver configuration remain essential. Verify the SLC64A ball pattern and reference layout against the actual PCB before release.
Recommended
Embedded Graphical Control Panels
Embedded control panels often connect a Linux-capable processor or programmable controller to a compact color display over a compact physical interface. The DS90C383SLC provides the transmitter half of such a link, using its 3.3-V operation, 24-bit parallel input, and programmable configuration to adapt the source interface to an LVDS receiver. Differential signaling can improve noise immunity in enclosure-mounted products where display cables run near switching power stages or motors. The engineer must still budget adequate board area for the BGA escape routing, power decoupling, and controlled-impedance output pairs. Receiver interoperability and allowable cable length are not supplied in the verified excerpts, so prototype signal-integrity validation is recommended before extending the design to production.
Recommended
Test and Measurement Front Panels
The DS90C383SLC can serve as the display-link transmitter in bench instruments and automated test equipment where a controller drives a remote or high-resolution screen. A 24-bit path and 65-MHz maximum clock suit display data transfer, while LVDS differential outputs can improve robustness over longer interconnects than an unprotected single-ended bus. The design should maintain a continuous reference plane beneath the output pairs, use datasheet-compliant differential impedance, and provide a nearby 3.3-V decoupling network. Instrument designers should test the complete source-to-panel channel for receiver lock, command timing, and cable susceptibility. The verified data does not include the DS90C383SLC's jitter, skew, or output-termination values, so those specifications should be obtained directly from the TI datasheet before making margin calculations.
Recommended
Point-of-Sale and Retail Terminals
Retail terminals, kitchen displays, and compact point-of-sale equipment can use the DS90C383SLC when the host controller requires a parallel display source and the display module accepts an LVDS link. The 24-bit interface provides ample pixel capacity, and the 65-MHz clock ceiling gives the integrator a defined target for a 24-bit FPD-Link implementation. Differential signaling is useful in commercial equipment where USB, display, and power connections may be bundled near one another. Integration still requires checking receiver lane mapping, data polarity, sync signals, and supported resolution at the target clock. Mechanical shock and temperature requirements are not stated in the supplied excerpts, so enclosure temperature testing and component-qualification review remain necessary before volume deployment.
Recommended
Video-Capture and Imaging Workstations
Imaging workstations can place the DS90C383SLC between a frame-processing engine and a local diagnostic display when the display interface uses an FPD-Link-compatible receiver. Its 3.3-V operation, 24-bit parallel input, and programmable behavior make it suitable for transferring high-volume display data without exposing a wide single-ended bus beyond the device boundary. Differential routing can reduce radiated emissions and improve noise immunity in systems containing high-speed processors and storage. The implementation should preserve the differential pair's geometry through connector escape paths and keep the output return path continuous. Pixel-clock, synchronization, and receiver-format compatibility must be proven with the selected panel because the verified snippets do not expose programmable timing details. A prototype channel test is advisable before fixing cable length and enclosure grounding.
Recommended
Recommended Products Summary
Engineering reference data for DS90C383SLC — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DS90C385A | DS90C383A | DS90C385 |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | SLC64A, 64-ball BGA, 8 mm x 8 mm | SLC64A, 64-ball BGA, 8 mm x 8 mm | SLC64A, 64-ball BGA, 8 mm x 8 mm | SLC64A, 64-ball BGA, 8 mm x 8 mm |
| Product Type | 3.3-V programmable 24-bit FPD-Link LVDS transmitter | FPD-Link LVDS transmitter | FPD-Link LVDS transmitter | FPD-Link LVDS transmitter |
| Pin Compatibility | DS90C383 reference device | Pin-to-pin compatible with DS90C383 according to TI | Named by TI in the DS90C385A compatibility statement | Named by TI in the DS90C385A compatibility statement |
| Documented Replacement Status | Original DS90C383 family device | TI identifies the part as a pin-to-pin replacement | Related family part | Related family part |
Key Differentiators
- Direct manufacturer-documented replacement path (vs DS90C385A)
- Complete 24-bit display data path (vs DS90C385A)
- Low-voltage 3.3-V system integration (vs DS90C383A)
- Verified distributor availability (vs DS90C385A)
Design Notes
Route the LVDS differential outputs as a tightly coupled pair over a continuous reference plane. The verified distributor data identifies the SLC64A package as an 8 mm by 8 mm BGA, so BGA escape routing, via symmetry, and connector transition geometry require careful review. Do not route the differential signals over split planes or introduce unequal serpentine lengths. The supplied excerpts do not specify the required trace impedance, output differential voltage, or recommended termination, so use the manufacturer datasheet and reference layout rather than generic values.
Design the 3.3-V rail for both the DS90C383SLC and the attached receiver without allowing the transmitter's digital transitions to corrupt the display link. Place local decoupling immediately between the relevant supply and ground balls, maintain a low-impedance ground connection, and keep return currents beneath the signal paths. The verified excerpts provide no capacitor values, allowable supply ripple, or current limit, so those values must be obtained from the TI datasheet before releasing the power network.
Do not treat a family relationship as proof that every ordering suffix is interchangeable. TI explicitly describes the DS90C385A as a pin-to-pin replacement for DS90C383-family devices, but the board still needs the correct package code, ball map, temperature grade, and receiver configuration. Check that the replacement preserves the 3.3-V supply, 24-bit data width, 65-MHz operating limit, and existing output termination. Use controlled engineering change and regression testing rather than substituting solely by distributor availability.
Validate the complete link from the graphics source through the transmitter, connector or cable, and LVDS receiver. Include tests for receiver lock, data corruption, command repeat, differential jitter margin, and conducted or radiated emissions under the final enclosure. The supplied source data does not state jitter, skew, rise-time, or cable-length limits, and the device is older than current display interfaces. Therefore, the 65-MHz clock figure is a maximum operating reference rather than proof that every cable, connector, or panel can operate at that frequency.
Compliance Information
The supplied TI product-page, distributor, and search-result snippets do not state the compliance status of DS90C383SLC. No compliance claim has been inferred. Confirm RoHS, REACH, lead-free, halogen-free, conflict-minerals, and AEC-Q100 status from current manufacturer documentation before qualification.
