DSPIC33EP128GP502-H/SP - 16-bit DSC 60 MIPS 128KB Flash | Microchip
MPN: DSPIC33EP128GP502-H/SP ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6.42 | $6.42 |
| 10 | $5.86 | $58.60 |
| 100 | $5.21 | $521.00 |
| 500 | $4.79 | $2,395.00 |
| 1,000 | $4.38 | $4,380.00 |
DSPIC33EP128GP502-H/SP Overview
A digital signal controller combines a microcontroller's peripheral set with DSP-engine math capability in one silicon device. In the power-management hierarchy, the DSC sits between a general-purpose MCU and a dedicated DSP: it executes real-time control loops (PID, filters, transforms) while simultaneously handling communication, timing, and analog sensing, making it a single-chip alternative to MCU-plus-DSP two-chip designs.
Key features include a 16-bit modified Harvard architecture with DSP instruction support (MAC, modulo addressing), high-speed PWM outputs suited for digital power conversion, up to 85°C-capable commercial temperature in the -H grade, and a rich general-purpose peripheral set including UART, SPI, and I2C serial interfaces. The 128 KB self-programmable Flash supports field firmware updates, and 16 KB of SRAM provides headroom for control loops and buffering.
Architecturally, the dsPIC33E pipeline is optimized for C-compiler efficiency with hardware loop support and single-cycle MAC operations, so control algorithms written in ANSI C achieve near-DSP throughput. The Peripheral Trigger Generator and DMA reduce CPU interrupt load in high-rate sampling systems.
Typical applications include industrial automation and motor control, switch-mode power supplies and digital power, and embedded sensing or audio signal processing where the through-hole 28-pin SPDIP package simplifies prototyping and low-volume production.
Design consideration: keep VDD and AVDD decoupled with 0.1 uF ceramics close to each pin and respect PGECx/PGEDx pairing for ICSP programming.
This page adds value beyond the datasheet by consolidating distributor pricing, pin-compatible same-family alternatives, and practical design notes in one place.
Drop-in alternatives for DSPIC33EP128GP502-H/SP — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33EP128GP502-H/SP (same form factor and footprint) — differing in ADC, Package, Timers.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33EP128GP502-I/SP
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33EP256GP502-I/SP
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33EP64GP502-I/SP
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$3.55 / Unit
View Datasheet →PIC24EP128GP202-I/SP
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33EP128GP502-H/SP Maximum Ratings & Electrical Characteristics
| Core Type | 16-bit dsPIC33E DSC |
| Max CPU Speed | 60 MIPS |
| Flash Program Memory | 128 KB |
| SRAM | 16 KB |
| Supply Voltage | 3.0 V to 3.6 V |
| Package | 28-pin SPDIP |
| Mounting Type | Through Hole |
| Timers | 5 x 16-bit |
| Input Capture Channels | 4 |
| Output Compare / PWM Channels | 4 |
| UART Channels | 2 |
| SPI Channels | 2 |
| I2C Channels | 2 |
| CAN | No (GP502 General Purpose family) |
| ADC | 10-bit, 1.1 Msps |
| Programming Interface | ICSP (2-wire, PGECx/PGEDx pairs) |
DSPIC33EP128GP502-H/SP Pin Configuration
| Pin 1 | MCLR — Master clear (reset) input, programming voltage in ICSP |
| Pin 2 | AN0/VREF+/CN3/RB0 — Analog input 0 / positive voltage reference / change notification |
| Pin 3 | AN1/VREF-/CN2/RB1 — Analog input 1 / negative voltage reference / change notification |
| Pin 4 | PGED1/AN2/C1IN-/CN4/RB2 — ICSP data 1 / analog input 2 / comparator input |
| Pin 5 | PGEC1/AN3/C1IN+/CN5/RB3 — ICSP clock 1 / analog input 3 / comparator input |
| Pin 6 | AN4/C1IN-/CN6/RB4 — Analog input 4 / comparator input |
| Pin 7 | VDD — Positive supply (3.0 V to 3.6 V) |
| Pin 8 | VSS — Ground reference |
| Pin 9 | OSC1/CLKI/RC12 — Crystal oscillator input / external clock input |
| Pin 10 | OSC2/CLKO/RC15 — Crystal oscillator output / clock output |
| Pin 11 | AN5/C1IN+/RP1/RC1 — Analog input 5 / comparator input / remappable peripheral pin |
| Pin 12 | AN6/OCFA/RP2/RC2 — Analog input 6 / output-compare fault / remappable pin |
| Pin 13 | AN7/RP3/RC3 — Analog input 7 / remappable peripheral pin |
| Pin 14 | VDD — Positive supply (3.0 V to 3.6 V) |
| Pin 15 | VSS — Ground reference |
| Pin 16 | SOSCI/CN1/RB6 — Secondary oscillator input / change notification |
| Pin 17 | SOSCO/T1CK/CN0/RB7 — Secondary oscillator output / Timer1 external clock |
| Pin 18 | T2CK/IC7/RP5/RB5 — Timer2 external clock / input capture 7 / remappable pin |
| Pin 19 | IC8/CTED2/RP6/RB8 — Input capture 8 / charge-time measurement / remappable pin |
| Pin 20 | CTED1/RP7/RB9 — Charge-time measurement / remappable peripheral pin |
| Pin 21 | PGED3/ASDA1/RP10/RB10 — ICSP data 3 / alternate I2C data / remappable pin |
| Pin 22 | PGEC3/ASCL1/RP11/RB11 — ICSP clock 3 / alternate I2C clock / remappable pin |
| Pin 23 | AN12/RP12/RB12 — Analog input 12 / remappable peripheral pin |
| Pin 24 | AN11/RP13/RB13 — Analog input 11 / remappable peripheral pin |
| Pin 25 | AN10/RP14/RB14 — Analog input 10 / remappable peripheral pin |
| Pin 26 | AN9/RP15/RB15 — Analog input 9 / remappable peripheral pin |
| Pin 27 | AVSS — Analog ground reference |
| Pin 28 | AVDD — Analog positive supply |
Typical Applications
DSPIC33EP128GP502-H/SP is suitable for 6 applications: Industrial Automation and Control, Digital Power Conversion, Embedded Sensing and Data Acquisition, Motor Control (Small Drives), Audio and Signal Processing, Educational and Prototyping Platforms.
Industrial Automation and Control
In factory automation nodes, the DSPIC33EP128GP502-H/SP pairs a 60 MIPS control core with dual UART/SPI/I2C interfaces to bridge sensors, actuators, and host controllers. Its 128 KB Flash holds protocol stacks and control state machines, while 16 KB SRAM buffers communication frames and sampled data. The through-hole 28-pin SPDIP package simplifies replacement in legacy DIN-rail and backplane boards designed for DIP microcontrollers. The five 16-bit timers coordinate multi-axis timing tasks, and the 10-bit ADC digitizes process variables. Deterministic interrupt latency keeps loop timing stable under full serial loading, an important factor when the same silicon also runs operator-interface code.
Recommended
Digital Power Conversion
The dsPIC33E core executes voltage-mode or current-mode SMPS control loops at the 60 MIPS ceiling, with the output compare/PWM channels generating switching waveforms and the 10-bit ADC sampling feedback. DSP MAC instructions accelerate compensator math (biquad filters, PID) written in ANSI C. The 128 KB Flash stores multiple converter profiles selectable at runtime, useful in programmable laboratory supplies and battery chargers. For peak-performance digital power with phase-shift PWM and fault protection, Microchip recommends the GM/MP families, but the GP502 handles moderate-frequency converters effectively. Place the device away from the switching stage and use Kelvin grounding to protect ADC accuracy from switching noise.
Recommended
Embedded Sensing and Data Acquisition
As an acquisition front end, the DSPIC33EP128GP502-H/SP samples analog channels via its integrated 10-bit ADC while DSP addressing modes support real-time FIR/IIR filtering of the data stream. The 16 KB SRAM supports block buffering before upload over UART or SPI to a host or gateway, and DMA offloads transfers to keep the CPU free for filtering. The 128 KB Flash retains calibration tables and logging across power cycles thanks to self-programmable memory. The through-hole SPDIP package is popular in laboratory instrumentation where hand-replacement and socketing matter. For higher resolution, an external SPI ADC such as the MCP3204 can be added on the existing SPI port.
Recommended
Motor Control (Small Drives)
For small BLDC, stepper, and brushed motor drives, the GP502 generates commutation waveforms on its PWM/compare channels while input captures decode hall sensors or encoder pulses. The 60 MIPS core runs commutation and speed-loop algorithms in C with cycle budget to spare, and the 128 KB Flash supports sensorless algorithms (back-EMF observers) that require more code than hall-based control. Four input-capture channels provide simultaneous timing of multiple feedback edges. Designers needing advanced dead-time insertion and fault shutdown for high-current drives should evaluate the dsPIC33EP GM family, but for low-voltage tool and appliance drives the GP502 provides a single-chip, low-cost controller with adequate throughput.
Recommended
Audio and Signal Processing
The single-cycle MAC, dual-fetch architecture, and hardware loop support of the dsPIC33E core make the GP502 capable of real-time audio tasks such as tone generation, equalization, active crossover filtering, and DTMF detection at consumer-audio sample rates. The 16 KB SRAM accommodates delay lines and coefficient sets for multi-band filters, while the 128 KB Flash stores effects or codec tables. UART and SPI links transport audio control data or stream samples to external converters. Because throughput is shared with control duties, budget MIPS carefully: heavy 24-bit processing may require sample-rate reduction. This makes the part well suited to embedded audio accessories and industrial sound annunciators rather than hi-fi production gear.
Recommended
Educational and Prototyping Platforms
The 28-pin SPDIP through-hole package of the -H/SP variant makes the dsPIC33EP128GP502 ideal for university labs, breadboarding, and single-layer prototype boards where hand soldering and socketed ICs are required. Students program it with MPLAB X and the free XC16 compiler using low-cost PICkit tools via the 2-wire ICSP interface. The 128 KB Flash tolerates repeated reprogramming during coursework, and the 60 MIPS core demonstrates both MCU-style I/O and DSP concepts (filters, transforms) on one chip. Because the footprint matches the broader dsPIC33EP/PIC24EP GP202/GP502 family, a lab board can accommodate 64 KB, 128 KB, or 256 KB variants without redesign.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33EP128GP502-H/SP — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33EP128GP502-I/SP | DSPIC33EP256GP502-I/SP | DSPIC33EP64GP502-I/SP | PIC24EP128GP202-I/SP |
|---|---|---|---|---|---|
| Package | 28-pin SPDIP | 28-pin SPDIP - same | 28-pin SPDIP - same | 28-pin SPDIP - same | 28-pin SPDIP - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Flash Program Memory | 128 KB | 128 KB | 256 KB | 64 KB | 128 KB |
| Max CPU Speed | 60 MIPS | 60 MIPS | 60 MIPS | 60 MIPS | 60 MIPS |
| Core / DSP Instructions | dsPIC33E with DSP engine | dsPIC33E with DSP engine | dsPIC33E with DSP engine | dsPIC33E with DSP engine | PIC24E MCU (no DSP instructions) |
| Supply Voltage | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| Lifecycle Status | Active (In Production) | Active | Active | Active | Active |
Key Differentiators
- DSP engine with single-cycle MAC at 60 MIPS (vs PIC24EP128GP202-I/SP)
- Double the program memory at the same footprint (vs DSPIC33EP64GP502-I/SP)
- Industrial temperature option in the same die (vs DSPIC33EP128GP502-I/SP)
Design Notes
Decouple every VDD pin (pins 7 and 14) with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, plus one 4.7 uF to 10 uF bulk capacitor per board. AVDD (pin 28) must be filtered separately - use an RC or ferrite bead plus 0.1 uF from VDD - so the 10-bit ADC sees a quiet analog rail. Tie AVSS (pin 27) to a clean analog ground node connected to VSS at a single point to prevent digital return currents from corrupting ADC readings.
ICSP programming requires matched PGECx/PGEDx pairs: if the programmer clock connects to PGEC1 (pin 5), the data line must use PGED1 (pin 4). Mixing pairs from different indexes is a frequent cause of 'device not found' errors. Also, MCLR (pin 1) needs a 10 kohm pull-up to VDD and must never be driven above the pin's rating when the programming voltage is applied; include a series resistor (approximately 100 ohm) if an external reset switch or supervisor drives the node.
Operating from a 3.3 V rail, core current scales with the 60 MIPS clock: budget a few tens of milliamps per the electrical characteristics section of the datasheet for the exact figure at your chosen oscillator configuration. Estimated: at 60 MIPS the device alone typically draws on the order of 40-60 mA, so size the 3.3 V regulator for the full peripheral load plus 50% margin. Unused remappable RP pins should be configured as outputs driven low or inputs with pull-ups to prevent floating-node EMI.
Compliance Information
Compliance data not present in the provided web data; verify RoHS/REACH status on the Microchip product page or distributor environmental data before design-in.
