DSPIC33EP128MC502-I/SO - 70 MIPS 16-bit DSC 128KB Flash | Microchip
MPN: DSPIC33EP128MC502-I/SO ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4.62 | $4.62 |
| 10 | $4.2 | $42.00 |
| 100 | $3.86 | $386.00 |
| 500 | $3.55 | $1,775.00 |
| 1,000 | $3.29 | $3,290.00 |
DSPIC33EP128MC502-I/SO Overview
A digital signal controller combines the computational architecture of a digital signal processor with the peripheral set and ease of use of a microcontroller. Within the power-management hierarchy, a DSC such as the dsPIC33EP family sits between general-purpose MCUs and dedicated DSPs, offering single-cycle MAC and DSP instructions alongside familiar control peripherals, making it the natural choice for embedded motor control and digital power conversion.
Key features include high-speed PWM modules for motor control and digital power, integrated analog peripherals, CAN, I2C, SPI, and UART connectivity, and industrial temperature operation from -40C to +85C denoted by the I temperature suffix. According to the Microchip product page, the dsPIC33EP family enables high-performance precision motor control systems that are more energy efficient and quieter in operation, and can control brushless DC and permanent magnet motors.
The 70 MIPS dsPIC DSC core executes the instruction set with DSP engine support (single-cycle MAC, dual operand fetch), while flash memory of 128 KB provides ample space for field-oriented control (FOC) firmware, communication stacks, and bootloaders. Self-programming flash supports in-circuit firmware updates via ICSP programming through any PGECx/PGEDx pin pair.
Typical applications include brushless DC and PMSM motor drives, digital switching power supplies (PFC, LLC), solar inverters, sensor-based embedded systems, and industrial automation nodes requiring CAN or UART connectivity.
A key design consideration: the internal core voltage is generated from the 3.3 V supply and requires a low-ESR capacitor on the VCAP/VDDCORE pin (pin 15); all VDD/VSS pairs must be decoupled, and both PGEC/PGED pins must be used as matched pairs during ICSP programming or debugging.
This page synthesizes distributor pricing, drop-in same-family alternatives, pinout details, and practical design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for DSPIC33EP128MC502-I/SO — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33EP128MC502-I/SO (same form factor and footprint) — differing in Package, Core Architecture, Operating Temperature, RAM, SRAM.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33EP256MC502-I/SO
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33EP128MC202-I/SO
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$3.92 / Unit
View Datasheet →DSPIC33EP64MC502-I/SO
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33EP32MC502-I/SO
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$2.66 / Unit
View Datasheet →DSPIC33EP128GP502-H/SO
✅ Drop-In✓ In Stock
$3.36 / Unit
View Datasheet →DSPIC33EP128MC502-I/SO Maximum Ratings & Electrical Characteristics
| Core Architecture | 16-bit dsPIC DSC |
| Max CPU Speed | 70 MIPS |
| CPU Frequency | 60 MHz (per Mouser listing) |
| Flash Program Memory | 128 KB (43K x 24) |
| RAM | 16 KB |
| Operating Voltage | 3.0 V to 3.6 V |
| Package | 28-SOIC (0.295 in, 7.50 mm width) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +85C (I grade) |
| Communication Interfaces | CAN, I2C, SPI, UART |
| Peripherals | High-Speed PWM, Advanced Analog, Op Amps (family feature) |
| Series | dsPIC33EP128MC502 (dsPIC 33EP) |
| Programming Interface | ICSP (2-wire, PGECx/PGEDx pairs) |
| Debug Support | Yes (multiple PGECx/PGEDx pairs) |
| RoHS Status | Compliant |
| Toolchain Support | MPLAB X IDE, SEGGER J-Link supported |
| Supply Voltage Class | 3.3 V logic |
DSPIC33EP128MC502-I/SO Pin Configuration
| Pin 1 | MCLR — Master clear reset (active low), programming voltage input |
| Pin 2 | AN0/VREF+/CN0/RB0 — Analog input 0 / ADC positive reference / change notification / port B bit 0 |
| Pin 3 | AN1/VREF-/CN1/RB1 — Analog input 1 / ADC negative reference / change notification / port B bit 1 |
| Pin 4 | AN2/SS1/C2IN-/RP0/CN2/RB2 — Analog input 2 / SPI slave select 1 / comparator 2 inverting input / remappable pin RP0 |
| Pin 5 | AN3/C2IN+/RP1/CN3/RB3 — Analog input 3 / comparator 2 non-inverting input / remappable pin RP1 |
| Pin 6 | AN4/SOSCI/RP2/CN4/RB4 — Analog input 4 / secondary oscillator input / remappable pin RP2 |
| Pin 7 | AN5/SOSCO/RP3/CN5/RB5 — Analog input 5 / secondary oscillator output / remappable pin RP3 |
| Pin 8 | VSS — Ground reference |
| Pin 9 | OSC1/CLKI/CN6/RA2 — Primary oscillator input / external clock input |
| Pin 10 | OSC2/CLKO/RC15 — Primary oscillator output / clock output |
| Pin 11 | VDD — Power supply (3.0 V to 3.6 V) |
| Pin 12 | PGED1/AN6/RP4/CN12/RB6 — In-circuit debug/programming data 1 / analog input 6 / remappable pin RP4 |
| Pin 13 | PGEC1/AN7/RP5/CN13/RB7 — In-circuit debug/programming clock 1 / analog input 7 / remappable pin RP5 |
| Pin 14 | VSS — Ground reference |
| Pin 15 | VCAP/VDDCORE — CPU core voltage - requires low-ESR external capacitor to VSS |
| Pin 16 | RC13 — Port C bit 13 (remappable peripheral functions) |
| Pin 17 | RC14 — Port C bit 14 (remappable peripheral functions) |
| Pin 18 | RF4/RP24 — Port F bit 4 / remappable pin RP24 |
| Pin 19 | RF5/RP25 — Port F bit 5 / remappable pin RP25 |
| Pin 20 | VDD — Power supply (3.0 V to 3.6 V) |
| Pin 21 | RF0/RP15 — Port F bit 0 / remappable pin RP15 |
| Pin 22 | RF1/RP14 — Port F bit 1 / remappable pin RP14 |
| Pin 23 | PGED3/RP10/RB8 — In-circuit debug data 3 / remappable pin RP10 / port B bit 8 |
| Pin 24 | PGEC3/RP11/RB9 — In-circuit debug clock 3 / remappable pin RP11 / port B bit 9 |
| Pin 25 | RP12/RB10 — Remappable pin RP12 / port B bit 10 |
| Pin 26 | RP13/RB11 — Remappable pin RP13 / port B bit 11 |
| Pin 27 | AVDD — Analog power supply - filter from VDD for best ADC accuracy |
| Pin 28 | AVSS — Analog ground reference |
Typical Applications
DSPIC33EP128MC502-I/SO is suitable for 6 applications: Brushless DC / PMSM Motor Control, Digital Switching Power Supplies, CAN-Based Industrial Automation Nodes, Embedded Sensing and Signal Processing, Solar Micro-Inverters and Power Conversion, Appliance and HVAC Motor Drives.
Brushless DC / PMSM Motor Control
The DSPIC33EP128MC502-I/SO fits BLDC and permanent magnet synchronous motor drives because its 70 MIPS dsPIC33E core executes field-oriented control loops with single-cycle MAC instructions, while the MC-variant high-speed PWM produces complementary outputs with programmable dead time for three-phase inverters. The 128 KB flash holds the full FOC estimator, current/speed loops, and a CAN or UART supervisory stack. Placed as the sole MCU driving a gate-driver stage, it runs the inner current loop at 10-20 kHz and outer speed loops slower; unlike general-purpose MCUs, the DSP engine avoids hand-optimized assembly for the Park/Clarke transforms. Microchip documents this family explicitly for precision, energy-efficient motor control.
Recommended
Digital Switching Power Supplies
For digital power converters such as PFC, LLC, and buck stages, the DSPIC33EP128MC502-I/SO provides the high-resolution PWM and fast ADC sampling needed for voltage-mode and current-mode closed-loop control at switching frequencies well into the hundreds of kilohertz. The 70 MIPS core leaves ample margin for compensator math, soft-start sequencing, and protection routines (overcurrent, overvoltage) executed in firmware. Running the control ISR from 128 KB flash avoids code-banking complexity common on smaller parts. Compared with an analog PWM controller, this DSC adds adaptive non-linear control, telemetry via UART/CAN, and firmware-updatable compensation - at the cost of firmware development effort and careful ADC sampling synchronization to the PWM period.
Recommended
CAN-Based Industrial Automation Nodes
The on-chip CAN module makes the DSPIC33EP128MC502-I/SO a compact industrial field node: one device handles CAN 2.0B communication, sensor acquisition via the integrated ADC, and local actuator PWM without external communication ICs. The industrial -40C to +85C rating matches factory-floor enclosures, and 128 KB flash accommodates a CANopen or proprietary protocol stack plus application logic. Typical usage is a distributed I/O or drive node sampling sensors at kilohertz rates and reporting over a 500 kbps CAN bus; deterministic interrupt latency of the dsPIC33E core supports hard real-time response. Versus an MCU plus separate CAN controller, integration reduces BOM cost and board area while simplifying EMC layout.
Recommended
Embedded Sensing and Signal Processing
With its DSP engine (single-cycle MAC, dual operand fetch, modulo and bit-reversed addressing), the DSPIC33EP128MC502-I/SO performs onboard digital filtering, FFT-based analysis, and sensor compensation locally, transmitting only processed results over SPI, I2C, or UART. The 16 KB RAM supports reasonable filter and buffer structures, and 128 KB flash stores calibration tables and multiple operating profiles. Typical deployment: a vibration or acoustic sensor front end sampled by the internal ADC and band-filtered in an FIR routine at tens of kilohertz. Compared with offloading to a host processor, local DSP reduces bus traffic and latency; compared with a pure DSP, this DSC retains full microcontroller peripherals for system supervision in one chip.
Recommended
Solar Micro-Inverters and Power Conversion
Grid-tied micro-inverter and DC-DC MPPT stages benefit from the DSPIC33EP128MC502-I/SO combination of high-speed PWM, fast 10/12-bit ADC with simultaneous sampling capability in the family, and 70 MIPS of headroom for MPPT algorithms running alongside the current control loop. Firmware executes phase-shifted full-bridge or interleaved buck modulation with cycle-by-cycle overcurrent protection in hardware. The 128 KB flash supports MPPT, grid monitoring logic, and a UART/CAN reporting link simultaneously. Design consideration: synchronize ADC sampling to PWM center points to avoid switching-noise corruption of current readings, and verify that interrupt jitter stays well below the switching period for stable loop response in high-frequency stages.
Recommended
Appliance and HVAC Motor Drives
Compressor, fan, and pump drives in appliances and HVAC systems use the DSPIC33EP128MC502-I/SO for sensorless BLDC control with the MC-variant PWM and analog comparators supporting low-cost single-shunt current sensing. The industrial temperature range and RoHS-compliant 28-SOIC package suit sealed controller boards, and 128 KB flash leaves room for field-updatable firmware, acoustic-noise-reduction modulation schemes, and fault diagnostics. Running sensorless back-EMF or sliding-mode observers on the DSP engine eliminates Hall sensors, reducing motor cost. Compared with discrete analog control, the DSC enables soft-start profiles and efficiency optimization; the trade-off is the need for careful firmware validation against stall and out-of-step conditions in low-cost, high-volume products.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33EP128MC502-I/SO — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33EP256MC502-I/SO | DSPIC33EP128MC202-I/SO | DSPIC33EP64MC502-I/SO | DSPIC33EP32MC502-I/SO | DSPIC33EP128GP502-H/SO |
|---|---|---|---|---|---|---|
| Package | 28-SOIC (7.50 mm) | 28-SOIC (7.50 mm) - same | 28-SOIC (7.50 mm) - same | 28-SOIC (7.50 mm) - same | 28-SOIC (7.50 mm) - same | 28-SOIC (7.50 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Flash Program Memory | 128 KB (43K x 24) | 256 KB | 64 KB | 64 KB | 32 KB | 128 KB |
| RAM | 16 KB | 16 KB | 16 KB | 16 KB | 16 KB | 16 KB |
| CPU Speed | 70 MIPS | 70 MIPS | 70 MIPS | 70 MIPS | 70 MIPS | 70 MIPS |
| Peripheral Variant | MC (Motor Control) | MC (Motor Control) | MC (Motor Control) | MC (Motor Control) | MC (Motor Control) | GP (General Purpose) |
| Operating Voltage | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
Key Differentiators
- Maximum flash in the 28-pin MC family (vs DSPIC33EP128MC202-I/SO)
- Growth path to double the code space (vs DSPIC33EP256MC502-I/SO)
- Motor-control-optimized peripheral set (vs DSPIC33EP128GP502-H/SO)
- Balanced cost/memory position (vs DSPIC33EP32MC502-I/SO)
Design Notes
The DSPIC33EP128MC502 derives its 1.8 V-class core supply internally from the 3.3 V VDD rail; pin 15 (VCAP/VDDCORE) must carry a low-ESR ceramic capacitor (value per datasheet, typically in the 10 uF class plus a ceramic) placed within a few millimeters of the pin. Omitting this capacitor or using a high-ESR part causes core brownouts and erratic resets. Connect both VDD pins (11, 20) and both VSS pins (8, 14); derive AVDD (27) through an RC or ferrite filter from VDD with AVSS (28) tied cleanly to ground for best ADC performance.
The device has three PGECx/PGEDx pairs for ICSP. Route one pair (e.g., PGEC1/PGED1 on pins 13/12) to a standard 5-pin ICSP header including MCLR, VDD, and VSS. Per Microchip programming guidance (see northernsoftware.com support notes), PGEC and PGED must be used as matched pairs - PGEC2 requires PGED2 - and all VDD/VSS pins must be connected during programming. Leave RB0-RB5 analog pins with resistor-isolated connections if they drive sensitive circuitry, since they toggle during programming/erase cycles.
Operating voltage is 3.0-3.6 V only - never connect a 5 V supply; if interfacing to 5 V logic, add level shifting or rely on the family's documented 5 V-tolerant digital inputs only where the datasheet permits. Also note that flash endurance and erase granularity limit parameter storage: use the dedicated EEPROM emulation routines from Microchip application libraries rather than frequent raw flash writes, or wear will degrade the code partition. For motor drives, verify PWM dead-time configuration in hardware before enabling the output stage.
When using the primary oscillator above ~20 MHz with PLL to reach 70 MIPS, keep the crystal and load capacitors close to pins 9/10 with a ground guard ring; assign secondary oscillator pins (SOSCI/SOSCO on 6/7) only to the 32.768 kHz crystal for RTCC or leave as GPIO. Remappable RPx pins allow clean routing of UART/SPI away from the PWM lines - plan pin assignment before layout so high-current PWM traces on adjacent pins do not couple into analog inputs AN0-AN5.
Compliance Information
RoHS compliance per current Microchip production status reflected in DigiKey/Mouser/LCSC listings. REACH, halogen-free, and conflict-minerals declarations must be confirmed from official Microchip compliance documents for this exact ordering code.
