DSPIC33CK128MC106-I/MR - 16-bit 100MHz DSC 128KB Flash | Microchip
MPN: DSPIC33CK128MC106-I/MR β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5.12 | $5.12 |
| 10 | $4.61 | $46.10 |
| 100 | $4.1 | $410.00 |
| 500 | $3.69 | $1,845.00 |
| 1,000 | $3.28 | $3,280.00 |
DSPIC33CK128MC106-I/MR Overview
A digital signal controller combines the computational throughput of a DSP with the peripheral integration and ease of use of a microcontroller. Within the embedded hierarchy, the dsPIC33CK sits between general-purpose MCUs and dedicated DSPs, making it a power management IC-class solution for real-time control loops that need both fast math and rich analog peripherals on one chip.
Key features include operation at up to 100 MIPS from a 3V to 3.6V supply, 53 general-purpose I/O pins, a 20-channel 12-bit ADC, two 12-bit DACs, integrated op amps, high-speed PWM peripherals, and CAN Flexible Data-Rate (CAN FD) support for modern in-vehicle and industrial networking. The functional-safety (FuSa) oriented family documentation supports safety-relevant designs.
Architecturally, the single-core dsPIC33CK executes DSP-class multiply-accumulate instructions while the high-resolution PWM module generates gate-drive waveforms for power conversion, closing control loops with the fast ADC in microsecond-scale cycles. This tight CPU-PWM-ADC integration is what distinguishes the part from ordinary 16-bit MCUs.
Typical applications include digital power supplies, PFC stages, motor control (BLDC, PMSM, FOC), automotive and industrial CAN FD nodes, and high-performance general embedded systems where deterministic control and integrated analog reduce bill-of-materials count.
A key design consideration: the part requires a 3V to 3.6V rail and supports ICSP programming via any matched PGECx/PGEDx pair, which must be used as a pair during debugging.
This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for DSPIC33CK128MC106-I/MR β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
DSPIC33CK256MC106-I/MR
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
DSPIC33CK64MC106-I/MR
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
DSPIC33CK32MC106-I/MR
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
DSPIC33CK128MC106-I/MR Maximum Ratings & Electrical Characteristics
| Core | 16-bit dsPIC DSC |
| Maximum Speed | 100 MHz (100 MIPS) |
| Program Memory (FLASH) | 128KB (128K x 8) |
| Data Memory (RAM) | 16KB |
| Operating Voltage | 3 V to 3.6 V |
| I/O Pins | 53 |
| ADC Resolution | 12-bit |
| ADC Channels | 20 |
| DAC | 2 x 12-bit |
| Integrated Op Amps | Yes |
| PWM | High-Speed PWM |
| CAN | CAN Flexible Data-Rate (CAN FD) |
| Package | 64-QFN (9x9 mm) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +125C |
| Family Designation | dsPIC33CK, Functional Safety (FuSa) |
DSPIC33CK128MC106-I/MR 64-qfn (9x9 mm) Pin Configuration Guide
Pin configuration for DSPIC33CK128MC106-I/MR (64-qfn (9x9 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for DSPIC33CK128MC106-I/MR.
Refer to the datasheet for full pin configuration.
Typical Applications
DSPIC33CK128MC106-I/MR is suitable for 6 applications: Digital Power Supplies, Brushless Motor Control (BLDC/PMSM), Automotive CAN FD Nodes, Solar Micro-Inverters and PFC, Industrial Sensing and Analog Acquisition, High-Performance General Embedded Systems.
Digital Power Supplies
The DSPIC33CK128MC106-I/MR fits switch-mode power conversion because its high-speed PWM generates precisely timed gate waveforms while the 20-channel 12-bit ADC closes voltage and current feedback loops at microsecond intervals on the 100 MHz core. Its DSP multiply-accumulate instructions execute PID and compensator control laws deterministically, and the integrated op amps condition shunt-current signals without external amplifiers, reducing component count. Placed between the housekeeping supply and the gate drivers, the controller supervises soft-start, fault handling, and telemetry over CAN FD or UART. Unlike analog-control power stages, firmware-based control enables adaptive mode switching and field updates, at the cost of a 3V to 3.6V supply domain and careful analog grounding for ADC accuracy.
Recommended
Brushless Motor Control (BLDC/PMSM)
Field-oriented control of PMSM and BLDC motors demands fast current-loop sampling and high-resolution PWM - exactly what the dsPIC33CK128MC106-I/MR provides with its 100 MIPS core, complementary high-speed PWM outputs with dead-time insertion, and simultaneous-sampling 12-bit ADC channels. The integrated op amps amplify low-level phase-current shunt signals, and the 128KB flash holds sensorless observer algorithms (SMO or flux estimators) with margin. The controller drives three-phase inverter gate drivers directly at 3.3V logic, computing Clarke/Park transforms and PI current loops in the microsecond cycle required for smooth torque at high electrical speeds. Designers must budget CPU headroom for the faster PWM frequencies used at high pole counts and verify ADC sampling alignment with PWM centers.
Recommended
Automotive CAN FD Nodes
With an integrated CAN Flexible Data-Rate module, the DSPIC33CK128MC106-I/MR serves body-control, actuator, and sensor nodes on modern automotive and industrial networks, standing alone as a compact 64-QFN node at -40C to +125C. The CAN FD peripheral supports the higher data-phase throughput and 64-byte payloads that classical CAN lacks, while the 100 MIPS core runs application logic, diagnostics (UDS-style services), and network management concurrently. The 128KB flash accommodates protocol stacks plus application code, and the FuSa-oriented family documentation supports safety-relevant development processes. Place the controller behind a CAN FD transceiver with proper ESD protection; the 3V to 3.6V domain requires a load-dump-tolerant supply front end in vehicle environments.
Recommended
Solar Micro-Inverters and PFC
Power-factor-correction stages and solar micro-inverter control benefit from the dsPIC33CK128MC106-I/MR's combination of high-resolution PWM for low output distortion and a fast 12-bit ADC sampling grid-current waveforms. The 100 MHz core executes harmonic compensation and MPPT algorithms in real time, while 128KB of flash retains firmware for grid-code compliance routines. The two 12-bit DACs can generate reference or auxiliary waveforms for monitoring. In typical deployment the controller sits between sensing front ends and the gate-driver stage, closing current loops every switching cycle. Key trade-off: at high switching frequencies, ensure ADC conversion time and interrupt latency remain a small fraction of the PWM period to keep loop bandwidth high and THD low.
Recommended
Industrial Sensing and Analog Acquisition
The dsPIC33CK128MC106-I/MR acts as an integrated analog acquisition hub in industrial equipment: its 20-channel 12-bit ADC scans temperature, pressure, and current sensors, while the two 12-bit DACs and integrated op amps drive actuator references and condition signals locally - all without external data converters. The 100 MHz core applies filtering, calibration, and limit checking, streaming results over UART, SPI, or CAN FD to PLCs and SCADA systems. With 53 GPIOs it also sequences relays and reads digital status in the same 64-QFN footprint, consolidating what previously required separate analog front ends. For highest ADC accuracy, filter the analog supply, keep switching-noise sources away from ANx traces, and exploit simultaneous sampling of related channels.
Recommended
High-Performance General Embedded Systems
For general embedded products that outgrow 8-bit or entry 16-bit MCUs, the dsPIC33CK128MC106-I/MR offers 100 MIPS of 16-bit DSP throughput, 128KB flash, and 16KB RAM in one 64-QFN package, covering applications from test instruments to building automation. The enhanced peripherals - multiple UART, SPI, I2C ports, timers, input capture, and PWM - handle mixed workloads, while DSP instructions accelerate FFT-based analysis, digital filtering, and sensor fusion. Development uses Microchip's standard toolchain with ICSP/ICD debugging through any matched PGECx/PGEDx pin pair. Compared with a 32-bit MCU solution, the part offers deterministic single-cycle MAC performance and mature motor/power peripherals; the trade-off is a 3V to 3.6V supply domain and C-optimized 16-bit rather than 32-bit data paths.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33CK128MC106-I/MR β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33CK256MC106-I/MR | DSPIC33CK64MC106-I/MR | DSPIC33CK32MC106-I/MR |
|---|---|---|---|---|
| Package | 64-QFN (9x9 mm) | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Program Memory (FLASH) | 128KB | 256KB | 64KB | 32KB |
| RAM | 16KB | 16KB | 16KB | 16KB |
| Core Speed | 100 MHz (100 MIPS) | 100 MHz (100 MIPS) | 100 MHz (100 MIPS) | 100 MHz (100 MIPS) |
| ADC | 20-ch, 12-bit | 20-ch, 12-bit | 20-ch, 12-bit | 20-ch, 12-bit |
| CAN FD | Yes | Yes | Yes | Yes |
| Operating Temperature | -40C to +125C | -40C to +125C | -40C to +125C | -40C to +125C |
Key Differentiators
- Maximum flash in the MC106 drop-in family (vs DSPIC33CK64MC106-I/MR)
- Integrated op amps and dual 12-bit DACs (vs DSPIC33CK32MC106-I/MR)
- Simpler single-core architecture than dsPIC33CH dual-core siblings (vs DSPIC33CH64MP506T-I/PT)
Design Notes
Supply the DSPIC33CK128MC106-I/MR from a regulated 3.0V to 3.6V rail per the datasheet operating conditions. Decouple every VDD/VSS pin pair on the 64-QFN with 100 nF ceramics placed within 2 mm of the pins, plus 4.7-10 uF of bulk capacitance near the device. In digital-power designs where the same board hosts gate drivers, isolate the controller's analog supply with an RC or ferrite bead filter so PWM edge noise does not degrade the 12-bit ADC's effective resolution. The 64-QFN exposed paddle should be soldered to a grounded pour for thermal and ground integrity.
Route analog ADC input traces (ANx) away from high-speed PWM outputs and gate-drive loops; use a solid ground plane under the analog section and a single-point star connection to power ground. Keep the CAN FD transceiver within 20 mm of the CAN pins with a series-terminated stub to the bus connector. Reserve an ICSP header wired to one PGECx/PGEDx pair - Microchip documentation requires matched pairs (e.g., PGEC2 with PGED2), and mismatched pairing will block programming. Place 22-100 ohm series resistors on PWM outputs to controller gate-driver input charging currents if long traces are unavoidable.
Three frequent mistakes with this family: (1) operating the part below 3.0V - the specified range is 3V to 3.6V, and brownout below that can corrupt flash writes, so enable the brown-out reset; (2) mixing PGECx/PGEDx pair members during ICSP, which fails silently on some programmers; (3) assuming the 100 MIPS core leaves infinite headroom - at 20 kHz+ PWM with sensorless observers, budget CPU utilization carefully and verify with the debugger's profiling tools before finalizing the control-loop timing.
Compliance Information
The -I/MR suffix indicates industrial temperature grade (-40C to +125C). Compliance data (RoHS/REACH/lead-free) not explicitly present in the provided web data; verify on the Microchip product page.
