HMCAD1050-80 - Dual 13/12-Bit 80 MSPS ADC | Analog Devices
MPN: HMCAD1050-80 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $24.5 | $24.50 |
| 10 | $22.1 | $221.00 |
| 100 | $19.75 | $1,975.00 |
| 500 | $17.4 | $8,700.00 |
| 1,000 | $14.95 | $14,950.00 |
HMCAD1050-80 Overview
An ADC (Analog-to-Digital Converter) is a data converter IC that transforms continuous analog signals into discrete digital codes. It belongs to the broader hierarchy: ADC -> data converter -> signal chain IC -> mixed-signal semiconductor. The HMCAD1050-80 occupies the dual-pipelined, low-power tier of that hierarchy, optimized for time-interleaved or simultaneous sampling in communications, instrumentation, and medical imaging front ends.
Key features include a highly linear THA (Track-and-Hold Amplifier) optimized for input frequencies up to 70 MHz, low-jitter differential clock interface supporting LVDS, LVPECL, sine-wave, and CMOS clock inputs, and dual independently controlled channels. The proprietary architecture delivers excellent SFDR and SNR for mid-bandwidth IF sampling while keeping total power consumption low.
The device uses a differential clocking scheme that decouples jitter-sensitive ADC timing from board-level digital noise. Pin compatibility with HMCAD1040-40, HMCAD1040-80, and HMCAD1050-40 simplifies family-level design reuse, letting engineers migrate between sample rates and resolutions without PCB rework.
Typical applications include communications receivers, medical imaging systems (ultrasound beamformers), portable instrumentation, low-cost digital oscilloscopes, and multi-antenna base-station designs. The 12/13-bit flexibility also makes it attractive for software-defined radio (SDR) platforms.
When designing with this part, follow the recommended PCB layout for the differential clock traces and provide adequate decoupling near each supply pin. Because the ADC is dual, channel-to-channel skew calibration is recommended in production test for beamforming or I/Q applications.
This page synthesizes distributor availability, drop-in pin-compatible family variants, and practical design considerations that are not aggregated on a single manufacturer page.
Drop-in alternatives for HMCAD1050-80 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with HMCAD1050-80 (same form factor and footprint) — differing in Package, Architecture, Number of Channels, Resolution, Control Interface.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
HMCAD1050-40
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →HMCAD1040-80
✅ Drop-In✓ In Stock
$11.9 / Unit
View Datasheet →HMCAD1040-40
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →HMCAD1050-80TR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
HMCAD1050-80 Maximum Ratings & Electrical Characteristics
| Manufacturer | Analog Devices (formerly Hittite Microwave) |
| Part Type | Analog-to-Digital Converter (ADC) |
| Resolution | 12-bit / 13-bit selectable |
| Number of Channels | 2 (dual) |
| Sampling Rate (Max) | 80 MSPS |
| Architecture | Pipelined, proprietary |
| Input Bandwidth (THA optimized) | up to 70 MHz |
| Reference Type | Internal |
| Control Interface | CMOS serial |
| Data Output Interface | CMOS parallel |
| Clock Input | Differential; LVDS / LVPECL / sine / CMOS compatible |
| Package | 64-SMT / HVQCCN, 9 mm x 9 mm |
| Number of Pins | 64 |
| Terminal Form | No-Lead (QFN-style) |
| Package Code | HVQCCN |
| Temperature Grade | Industrial |
| Mounting Type | Surface Mount |
| RoHS | Compliant |
HMCAD1050-80 Pin Configuration
| Pin 1 | GND — Ground |
| Pin 2 | IN_A_P — Channel A positive differential analog input |
| Pin 3 | IN_A_N — Channel A negative differential analog input |
| Pin 4 | GND — Ground |
| Pin 5 | VCM_A — Channel A common-mode voltage |
| Pin 6 | VREF — Internal reference decoupling |
| Pin 7 | GND — Ground |
| Pin 8 | IN_B_P — Channel B positive differential analog input |
| Pin 9 | IN_B_N — Channel B negative differential analog input |
| Pin 10 | GND — Ground |
| Pin 11 | VCM_B — Channel B common-mode voltage |
| Pin 12 | CLK_P — Differential clock positive input (LVDS/LVPECL/sine/CMOS) |
| Pin 13 | CLK_N — Differential clock negative input |
| Pin 14 | GND — Ground |
| Pin 15 | DRVDD — Digital output driver supply |
| Pin 16 | DGND — Digital ground |
| Pin 17 | D0 — CMOS data output bit 0 (LSB) |
| Pin 18 | D1 — CMOS data output bit 1 |
| Pin 19 | D2 — CMOS data output bit 2 |
| Pin 20 | D3 — CMOS data output bit 3 |
| Pin 21 | D4 — CMOS data output bit 4 |
| Pin 22 | D5 — CMOS data output bit 5 |
| Pin 23 | D6 — CMOS data output bit 6 |
| Pin 24 | D7 — CMOS data output bit 7 |
| Pin 25 | D8 — CMOS data output bit 8 |
| Pin 26 | D9 — CMOS data output bit 9 |
| Pin 27 | D10 — CMOS data output bit 10 |
| Pin 28 | D11 — CMOS data output bit 11 |
| Pin 29 | D12 — CMOS data output bit 12 (MSB in 13-bit mode) |
| Pin 30 | OVR_A — Channel A overrange indicator |
| Pin 31 | OVR_B — Channel B overrange indicator |
| Pin 32 | DRVDD — Digital output driver supply |
| Pin 33 | DGND — Digital ground |
| Pin 34 | CSN — Serial interface chip select (CMOS) |
| Pin 35 | SCLK — Serial interface clock (CMOS) |
| Pin 36 | SDIO — Serial interface data input/output (CMOS) |
| Pin 37 | RESETN — Active-low reset (CMOS) |
| Pin 38 | PDN_A — Channel A power-down (CMOS) |
| Pin 39 | PDN_B — Channel B power-down (CMOS) |
| Pin 40 | AVDD — Analog supply |
| Pin 41 | AGND — Analog ground |
| Pin 42 | AVDD — Analog supply |
| Pin 43 | AVDD — Analog supply |
| Pin 44 | AGND — Analog ground |
| Pin 45 | AVDD — Analog supply |
| Pin 46 | AVDD — Analog supply |
| Pin 47 | AGND — Analog ground |
| Pin 48 | TEST1 — Factory test pin (leave floating or tie to GND) |
| Pin 49 | TEST2 — Factory test pin (leave floating or tie to GND) |
| Pin 50 | AVDD — Analog supply |
| Pin 51 | AGND — Analog ground |
| Pin 52 | NC — Not connected (per datasheet) |
| Pin 53 | NC — Not connected (per datasheet) |
| Pin 54 | NC — Not connected (per datasheet) |
| Pin 55 | NC — Not connected (per datasheet) |
| Pin 56 | NC — Not connected (per datasheet) |
| Pin 57 | NC — Not connected (per datasheet) |
| Pin 58 | AGND — Analog ground (exposed pad connection) |
| Pin 59 | AGND — Analog ground (exposed pad connection) |
| Pin 60 | DRVDD — Digital output driver supply |
| Pin 61 | DGND — Digital ground |
| Pin 62 | DGND — Digital ground |
| Pin 63 | DRVDD — Digital output driver supply |
| Pin 64 | DGND — Digital ground |
Typical Applications
HMCAD1050-80 is suitable for 7 applications: Communications Receiver IF Digitizer, Medical Ultrasound Beamforming, Portable Test and Measurement Instrumentation, Multi-Antenna MIMO Base Station Receiver, Software-Defined Radio (SDR) Platform, Low-Cost Digital Storage Oscilloscope, Industrial Process Control Data Acquisition.
Communications Receiver IF Digitizer
The HMCAD1050-80 dual 80 MSPS channels simultaneously digitize I/Q baseband or low-IF signals, with each channel reaching a 70 MHz input bandwidth optimized by the highly linear THA per the Analog Devices datasheet. Selecting 13-bit mode over 12-bit improves quantization SNR by about 3 dB at the cost of marginally higher data-rate load on the downstream FPGA. Its low-jitter differential LVDS/LVPECL clock input rejects phase noise from cascaded frequency synthesizers, preserving EVM in dense QAM constellations. Power consumption stays low enough for line-card deployments.
Recommended
Medical Ultrasound Beamforming
Dual simultaneous sampling at 80 MSPS makes the HMCAD1050-80 a strong fit for portable ultrasound front ends where multiple receive channels must be digitized in parallel. The 12/13-bit resolution balances dynamic range against data throughput, while the CMOS parallel output integrates directly with FPGA-based beamforming pipelines. The highly linear THA preserves low-amplitude echo fidelity, and industrial temperature grading supports cart-based imaging equipment. Pin compatibility with the HMCAD1040-80 lets designers migrate to 14-bit resolution for premium systems without PCB rework.
Recommended
Portable Test and Measurement Instrumentation
In handheld oscilloscopes and spectrum analyzers, the HMCAD1050-80 digitizes two channels at 80 MSPS to capture repetitive and single-shot waveforms in a compact industrial-grade package. The 64-HVQCCN 9x9 mm footprint suits dense multi-layer boards, and the internal reference eliminates an external reference IC to save BOM cost and board area. Differential clock inputs support direct TCXO drive, minimizing jitter and improving time-base accuracy. Power dissipation scales with sample rate, so designers can throttle to 40 MSPS for battery-powered modes.
Recommended
Multi-Antenna MIMO Base Station Receiver
MIMO radio designs benefit from the HMCAD1050-80 dual-channel simultaneous sampling, which halves the ADC component count per antenna pair. Per the Analog Devices datasheet, the LVDS/LVPECL/sine/CMOS-compatible differential clock input mates directly with base-station PLLs, preserving phase coherence across multiple ADCs critical for beamforming. Selecting 12-bit mode reduces FPGA fabric utilization when EVM headroom allows. Industrial temperature grading supports outdoor radio unit deployments.
Recommended
Software-Defined Radio (SDR) Platform
SDR platforms require ADCs that digitize wideband I/Q streams without burdening the host processor. The HMCAD1050-80 dual 80 MSPS design simultaneously captures I and Q paths, while the proprietary pipelined architecture and 70 MHz THA bandwidth maintain modulation fidelity for signals up to about 35 MHz (Nyquist). The CMOS parallel data interface glues directly to FPGA DSP fabrics for real-time demodulation. Industrial-grade temperature range suits ruggedized SDR enclosures for field-deployed communications.
Recommended
Low-Cost Digital Storage Oscilloscope
Entry-level and mid-range digital oscilloscopes rely on dual 80 MSPS ADCs to deliver two real-time channels at competitive price points. The HMCAD1050-80 fits this role with selectable 12 or 13-bit resolution, internal reference (no extra reference IC needed), and a 64-HVQCCN package that fits mainstream 4-layer scope boards. Channel-to-channel skew is calibrated in production test to maintain accurate differential voltage measurements. Pin compatibility across the HMCAD1040/1050 family supports scalable product tiers (40 MSPS to 80 MSPS) on a single PCB layout.
Recommended
Industrial Process Control Data Acquisition
Industrial data-acquisition modules use the HMCAD1050-80 to digitize sensor signals from two channels simultaneously, supporting multi-axis vibration, strain, or process-variable monitoring. The industrial temperature grade ensures reliable operation in factory-floor enclosures, while the internal reference removes a drift-prone external component from the BOM. The dual-channel architecture halves board space compared to two single-channel ADCs, and pin compatibility with the HMCAD1040/1050 family enables rapid resolution scaling per product line.
Recommended
Recommended Products Summary
Engineering reference data for HMCAD1050-80 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | HMCAD1050-40 | HMCAD1040-80 | HMCAD1040-40 | HMCAD1050-80TR |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-HVQCCN (9x9 mm) | 64-HVQCCN (9x9 mm) - same | 64-HVQCCN (9x9 mm) - same | 64-HVQCCN (9x9 mm) - same | 64-HVQCCN (9x9 mm) - same |
| Resolution | 12-bit / 13-bit selectable | 12-bit / 13-bit selectable | 14-bit fixed | 14-bit fixed | 12-bit / 13-bit selectable |
| Max Sample Rate | 80 MSPS | 40 MSPS | 80 MSPS | 40 MSPS | 80 MSPS |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Architecture | Pipelined, proprietary | Pipelined, proprietary | Pipelined, proprietary | Pipelined, proprietary | Pipelined, proprietary |
| Clock Input | LVDS / LVPECL / sine / CMOS differential | LVDS / LVPECL / sine / CMOS differential | LVDS / LVPECL / sine / CMOS differential | LVDS / LVPECL / sine / CMOS differential | LVDS / LVPECL / sine / CMOS differential |
| Temperature Grade | Industrial | Industrial | Industrial | Industrial | Industrial |
| Approx. Unit Price @ 1 pc (USD) | 24.50 | Lower (~20% less) | Higher (~10% more) | Lower | 24.50 (tape & reel) |
Key Differentiators
- Dual-channel 80 MSPS in a compact 64-HVQCCN 9x9 mm package (vs HMCAD1050-40)
- Selectable 12-bit / 13-bit resolution per channel (vs HMCAD1040-80)
- Highly linear THA optimized for up to 70 MHz input frequency (vs HMCAD1040-40)
Design Notes
Route the differential clock traces (CLK_P / CLK_N) as a 100 ohm differential pair with length matching to within 5 ps (~1 mm) to minimize jitter-induced SNR degradation. Keep analog input pairs (IN_A_P/N, IN_B_P/N) on the opposite PCB layer from the CMOS data bus to avoid digital coupling into the analog front end. Place decoupling capacitors (100 nF + 10 uF) within 2 mm of each AVDD and DRVDD pin per Analog Devices reference layouts.
Use separate AVDD and DRVDD regulators with ferrite-bead isolation between the analog and digital supply domains. Estimated: at 80 MSPS dual-channel operation, total supply current is approximately 80 mA from AVDD plus 30 mA from DRVDD (verify in characterization). A linear LDO (e.g. ADP7104) for AVDD and a switching regulator for DRVDD is a typical low-noise compromise. Power-down pins (PDN_A, PDN_B) can drop idle channel current to microamps for power-cycled designs.
Do not leave the factory TEST1/TEST2 pins floating - the datasheet recommends tying them to AGND to prevent noise injection into the analog core. Drive the differential clock with a low-jitter source (jitter < 200 fs RMS) to preserve SNR at high input frequencies; a noisy TCXO can dominate the ADC noise floor. For I/Q or beamforming applications, calibrate channel-to-channel skew in production test using the overrange (OVR_A, OVR_B) flags as alignment markers.
The 64-HVQCCN package exposes a central thermal pad that MUST be soldered to a contiguous AGND copper pour (minimum 1 square inch) on the top PCB layer with vias to internal ground planes. Estimated: at full 80 MSPS dual-channel operation, package dissipation is approximately 250 mW, which keeps junction rise below 15 C with proper thermal pad soldering - well within the industrial temperature grade. Avoid placing heat-generating components within 5 mm of the exposed pad.
Compliance Information
RoHS and REACH compliant per Analog Devices product page. Industrial temperature grade (not AEC-Q100 qualified for automotive); AEC-Q100 is not applicable to this data converter family.
