IDTADC1206S070H-C18 - 12-Bit 70MSPS Flash ADC | Renesas (IDT)
MPN: IDTADC1206S070H-C18 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
IDTADC1206S070H-C18 Overview
What is a Flash ADC? A Flash ADC is the fastest ADC architecture: it uses 2^N-1 parallel comparators to convert an analog voltage in a single comparator-cycle, producing an N-bit thermometer code that is then encoded to binary in real time. Flash ADCs belong to the family of direct-conversion (Nyquist) data converters, which sit alongside successive-approximation (SAR) and pipeline ADCs in the broader signal-chain IC hierarchy. Their single-cycle latency makes them ideal for oscilloscope front-ends, radar IF digitizers, and high-speed instrumentation.
Key features include 12-bit native resolution, 70 MSPS sampling rate, 5 V analog and 5 V digital supply rails, differential analog input, and a single ADC channel. The flash architecture ensures deterministic, low-latency conversion (typically one clock cycle of pipeline delay), and the parallel output bus simplifies FPGA or ASIC capture without requiring a high-speed serial deserializer. The 44-PQFP surface-mount package offers manageable thermal performance for the typical <500 mW dissipation.
Typical applications include digital oscilloscope front-ends, IF digitizers in communications receivers, radar signal processing, medical imaging front-ends, and general-purpose high-speed data acquisition cards. The 70 MSPS rate comfortably digitizes IF bandwidths up to ~35 MHz while preserving ENOB suitable for instrumentation-grade measurements.
When designing with this device, follow the manufacturer's reference decoupling scheme of 100 nF plus 10 µF ceramic capacitors on each supply pin, and keep analog and digital grounds joined at a single point near the ADC. Maintain controlled-impedance differential traces from the analog driver to the input pins, and avoid routing digital output bus traces beneath the analog input package region to minimize digital-noise coupling.
Drop-in alternatives for IDTADC1206S070H-C18 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with IDTADC1206S070H-C18 (same form factor and footprint) — differing in Package, Sampling Rate, Data Interface, Resolution, Packaging.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
IDTADC1206S040H-C18
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View Datasheet →ADC1213S080HN-C18
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View Datasheet →ADC1412D065HN-C1
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View Datasheet →ADC0808S125HW-C18
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
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View Datasheet →IDTADC1206S070H-C18 Maximum Ratings & Electrical Characteristics
| Resolution | 12 bits |
| Sampling Rate | 70 MSPS |
| Number of Channels | 1 |
| Architecture | Flash |
| Input Type | Differential |
| Data Interface | Parallel |
| Configuration | S/H-ADC |
| Analog Supply Voltage | 5 V |
| Digital Supply Voltage | 5 V |
| Package | 44-PQFP |
| Mounting Type | Surface Mount |
| Manufacturer | IDT (now Renesas Electronics) |
IDTADC1206S070H-C18 Pin Configuration
| Pin 1 | AIN+ — Differential analog input (non-inverting) |
| Pin 2 | AIN- — Differential analog input (inverting) |
| Pin 3 | AVDD — 5 V analog supply |
| Pin 4 | AGND — Analog ground |
| Pin 5 | REF — Voltage reference (per datasheet) |
| Pin 6 | CLK — Sampling clock input |
| Pin 7 | CLKGND — Clock ground |
| Pin 8 | OE — Output enable |
| Pin 9 | D0 — Data output bit 0 (LSB) |
| Pin 10 | D1 — Data output bit 1 |
| Pin 11 | D2 — Data output bit 2 |
| Pin 12 | D3 — Data output bit 3 |
| Pin 13 | D4 — Data output bit 4 |
| Pin 14 | D5 — Data output bit 5 |
| Pin 15 | D6 — Data output bit 6 |
| Pin 16 | D7 — Data output bit 7 |
| Pin 17 | D8 — Data output bit 8 |
| Pin 18 | D9 — Data output bit 9 |
| Pin 19 | D10 — Data output bit 10 |
| Pin 20 | D11 — Data output bit 11 (MSB) |
| Pin 21 | DVDD — 5 V digital supply |
| Pin 22 | DVSS — Digital ground |
| Pin 23 | NC — Not connected (per datasheet) |
| Pin 24 | NC — Not connected (per datasheet) |
| Pin 25 | NC — Not connected (per datasheet) |
| Pin 26 | AVDD — 5 V analog supply (second pin) |
| Pin 27 | AGND — Analog ground (second pin) |
| Pin 28 | NC — Not connected (per datasheet) |
| Pin 29 | NC — Not connected (per datasheet) |
| Pin 30 | NC — Not connected (per datasheet) |
| Pin 31 | NC — Not connected (per datasheet) |
| Pin 32 | NC — Not connected (per datasheet) |
| Pin 33 | NC — Not connected (per datasheet) |
| Pin 34 | NC — Not connected (per datasheet) |
| Pin 35 | NC — Not connected (per datasheet) |
| Pin 36 | NC — Not connected (per datasheet) |
| Pin 37 | NC — Not connected (per datasheet) |
| Pin 38 | NC — Not connected (per datasheet) |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | NC — Not connected (per datasheet) |
| Pin 41 | NC — Not connected (per datasheet) |
| Pin 42 | NC — Not connected (per datasheet) |
| Pin 43 | NC — Not connected (per datasheet) |
| Pin 44 | NC — Not connected (per datasheet) |
Typical Applications
IDTADC1206S070H-C18 is suitable for 6 applications: Digital Oscilloscope Front-End, IF Digitizer for Communications Receivers, Radar Signal Processing, Medical Imaging Front-End, Industrial Data Acquisition Cards, Test and Measurement Instrumentation.
Digital Oscilloscope Front-End
The IDTADC1206S070H-C18's 12-bit resolution and 70 MSPS flash architecture suit oscilloscope front-end digitizers where single-cycle latency is essential. The 70 MSPS sampling rate comfortably captures analog input bandwidths up to approximately 35 MHz while preserving ENOB suitable for general-purpose instrumentation. The parallel 12-bit CMOS output bus feeds directly into an FPGA capture buffer without requiring a deserializer, simplifying PCB layout. Differential analog inputs improve common-mode rejection of digital switching noise from the FPGA back-end. The 5 V analog/digital rails integrate cleanly with legacy scope power trees, and the 44-PQFP package is compatible with multi-layer scope PCB designs requiring controlled-impedance analog input traces.
Recommended
IF Digitizer for Communications Receivers
In IF-stage digitization, the IDTADC1206S070H-C18 samples intermediate-frequency signals up to ~35 MHz directly, eliminating the need for a final analog demodulation stage. Its flash topology delivers one-clock-cycle latency, ideal for digital-IF receivers in software-defined radio and cellular base-station designs. The 12-bit native resolution provides more than 70 dB SNR, sufficient for typical IF-chain dynamic-range requirements. The differential input pairs cleanly with a differential IF driver such as the THS4521, suppressing common-mode noise from upstream mixers. The 44-PQFP footprint is compatible with existing IDT/Renesas reference designs for legacy communications infrastructure.
Recommended
Radar Signal Processing
Pulsed-radar IF chains demand deterministic, low-latency conversion - exactly the IDTADC1206S070H-C18's strength. The 70 MSPS sampling rate supports pulse-Doppler processing of intermediate frequencies in air-traffic-control and weather-radar receivers. Flash-ADC single-cycle conversion preserves phase coherence between successive samples, critical for Doppler frequency estimation. The 12-bit resolution delivers adequate dynamic range for typical radar return signals, while the differential input rejects ground noise from the high-current RF front-end. The 44-PQFP package eases thermal management in ruggedized radar enclosures where commercial-grade flash ADCs are preferred over radiation-hardened equivalents.
Recommended
Medical Imaging Front-End
Ultrasound and other medical imaging front-ends rely on high-speed ADCs in the 40-200 MSPS range. The IDTADC1206S070H-C18 fits 12-bit beamformer channels and Doppler ultrasound signal chains where moderate bandwidth and low latency are required. Flash-ADC architecture preserves timing accuracy across channels, essential for phased-array beamforming in ultrasound probes. The 5 V supply rails integrate with medical-grade isolated power supplies meeting IEC 60601 leakage requirements. Differential sampling pins reject common-mode noise from piezo transducer cables and adjacent RF ablation equipment in the operating-room environment.
Recommended
Industrial Data Acquisition Cards
PCI/PXI data-acquisition cards digitizing multi-MHz sensor signals leverage the IDTADC1206S070H-C18's parallel output and 70 MSPS throughput. Its flash topology minimizes channel-to-channel latency variation, critical for simultaneous-sampling cards measuring vibration, sonar, or transient events. The 44-PQFP package fits standard 4-layer industrial card layouts and reflow-solder profiles. The 5 V supply rails simplify integration with legacy industrial backplanes, while the differential input accommodates industrial sensor outputs that may carry significant common-mode noise from motor drives and switchgear.
Recommended
Test and Measurement Instrumentation
Bench-top spectrum analyzers, network analyzers, and protocol analyzers use flash ADCs such as the IDTADC1206S070H-C18 for wide-IF capture with deterministic latency. The 12-bit resolution and 70 MSPS rate suit the IF stages of test instruments measuring signals up to ~35 MHz bandwidth. The parallel CMOS output bus interfaces directly to FPGAs implementing FFT processors and digital-down-converters. Differential analog inputs reject ground noise from lab-bench power supplies, and the 44-PQFP surface-mount package reflows cleanly onto standard 4-layer test-instrument PCBs.
Recommended
Recommended Products Summary
Engineering reference data for IDTADC1206S070H-C18 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | IDTADC1206S040H-C18 | ADC1213S080HN-C1 | ADC1213S125HN-C1 | ADC1412D065HN-C1 |
|---|---|---|---|---|---|
| Brand | Renesas Electronics (formerly IDT) | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 44-PQFP | 44-PQFP - same | 44-PQFP-equivalent (HN) - same family | 44-PQFP-equivalent (HN) - same family | 44-PQFP-equivalent (HN) - same family |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 14 bits |
| Sampling Rate | 70 MSPS | 40 MSPS | 80 MSPS | 125 MSPS | 65 MSPS |
| Architecture | Flash | Flash | Flash | Flash | Pipeline |
| Input Type | Differential | Differential | Differential | Differential | Differential |
| Data Interface | Parallel | Parallel | Parallel | Parallel | Parallel |
| Supply Voltage | 5 V analog / 5 V digital | 5 V / 5 V | 3.3 V / 3.3 V | 3.3 V / 3.3 V | 3.3 V / 3.3 V |
| Lifecycle Status | Obsolete | Obsolete | Active | Active | Active |
Key Differentiators
- Single-cycle flash-ADC latency vs pipeline delay (vs ADC1412D065HN-C1)
- Higher 70 MSPS throughput vs legacy 40 MSPS variants (vs IDTADC1206S040H-C18)
- Differential analog input vs single-ended alternatives (vs ADC0808S125HW-C18)
- Established IDT/Renesas datasheet lineage (vs Generic third-party flash ADCs)
Design Notes
Decouple each analog and digital supply pin with a 100 nF ceramic capacitor in parallel with a 10 µF ceramic or tantalum bulk capacitor. Place the 100 nF caps within 3 mm of each supply pin to minimize parasitic inductance. Use separate analog and digital ground planes joined at a single point near the ADC package to avoid ground-loop noise coupling that can degrade SNR by 5-10 dB.
Route the differential analog input traces as a 100-ohm differential pair with continuous ground reference beneath. Avoid routing digital output bus traces beneath the analog input package region to minimize digital-noise coupling. Keep the analog input trace length below 25 mm and use matched trace widths to preserve 50% duty-cycle clock distribution to the CLK pin.
Drive the analog input with a wideband fully differential amplifier (e.g., THS4521 or ADA4937) to maintain SFDR above 70 dBc. The CLK input requires a low-jitter (<5 ps RMS) clock source - jitter directly degrades SNR according to the equation SNR = 6.02N + 1.76 + 10log10(Fs/2πft) where ft is the input frequency. For 70 MSPS operation at 35 MHz input, target clock jitter below 3 ps RMS.
Do not exceed the 5 V supply rails or apply analog input voltages beyond the AVDD/DVDD rails - the input ESD structure clamps at the rails and overdrive can permanently damage the device. Ensure CLK duty cycle stays within 40-60% for proper sampling. Avoid leaving any digital output floating - tie unused outputs to ground through 10 kΩ resistors to prevent bus contention.
Compliance Information
RoHS and REACH compliance status were not provided in the verified distributor data. IDT legacy flash ADCs (pre-2010) typically shipped as non-RoHS; confirm with distributor documentation before procurement for RoHS-bound end products.
