LTC2144IUP-12 - 12-Bit 105Msps Dual ADC | Analog Devices
MPN: LTC2144IUP-12 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $78.5 | $78.50 |
| 10 | $70.2 | $702.00 |
| 100 | $60.4 | $6,040.00 |
| 500 | $53.8 | $26,900.00 |
| 1,000 | $47.2 | $47,200.00 |
LTC2144IUP-12 Overview
An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes. Pipelined ADCs use a multi-stage architecture to achieve high sample rates (tens to hundreds of Msps) while keeping per-stage hardware compact; dual simultaneous-sampling ADCs capture two channels at exactly the same instant, eliminating channel-to-channel skew in I/Q or diversity receivers. Within the power management and data-converter taxonomy, the LTC2144IUP-12 belongs to high-speed pipelined ADCs -> data converters -> mixed-signal ICs -> integrated circuits.
Key features of this part include 105 Msps per channel sample rate, 12-bit resolution, 70.6 dB SNR, 89 dB SFDR, 0.08 ps RMS aperture jitter, and a parallel CMOS/LVDS output interface selectable per channel. The 64-QFN (UP) exposed-pad package provides low thermal resistance (~28 C/W theta_JC via the pad), enabling operation across the industrial -40C to +85C temperature range.
The pipelined architecture uses 12 internal stages with per-stage flash sub-ADC and MDAC residue amplification; sample-and-hold is on-chip and front-end differential, supporting 1 Vp-p to 2 Vp-p full-scale inputs. A separate output supply (OVDD) lets the digital outputs drive 1.8V to 3.3V logic while the analog core runs from 1.8V.
Typical applications include communications receivers, cellular base-station digitizers, radar/sonar signal chains, medical imaging front-ends, and portable test instrumentation. Designers commonly pair it with the AD8138 differential driver at the input and an FPGA for the parallel data capture.
Design trade-off: at 105 Msps with 1.8V analog supply, expect roughly 100 mW per channel dissipation. Use the exposed pad with a continuous ground plane and bypass AVDD with 10 uF + 0.1 uF ceramic as close as possible to each pin pair.
This page synthesizes distributor pricing, drop-in same-package alternatives, and application-specific design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for LTC2144IUP-12 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2144IUP-12 (same form factor and footprint) — differing in Package, Resolution, RoHS Status, SFDR, SNR.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2145IUP-12#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2143IUP-12#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2144CUP-12#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2144IUP-14#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2142IUP-14
✅ Drop-In✓ In Stock
$34.71 / Unit
View Datasheet →LTC2144IUP-12 Maximum Ratings & Electrical Characteristics
| Resolution | 12 bits |
| Sample Rate per Channel | 105 Msps |
| Number of Channels | 2 (simultaneous sampling) |
| Architecture | Pipelined |
| Input Type | Differential, 1 Vp-p to 2 Vp-p full-scale |
| SNR | 70.6 dB |
| SFDR | 89 dB |
| Aperture Jitter | 0.08 ps RMS |
| Output Interface | Parallel CMOS or LVDS (selectable per channel) |
| Analog Supply Voltage (AVDD) | 1.8 V |
| Output Supply Voltage (OVDD) | 1.8 V to 3.3 V |
| Operating Temperature Range | -40C to +85C (industrial, 'I' grade) |
| Package | 64-pin QFN (UP) 9x9 mm with exposed pad |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (#PBF suffix) |
LTC2144IUP-12 Pin Configuration
| Pin 1 | GND — Ground |
| Pin 2 | AIN1+ — Channel 1 differential input positive |
| Pin 3 | AIN1- — Channel 1 differential input negative |
| Pin 4 | GND — Ground |
| Pin 5 | VCM1 — Channel 1 common-mode voltage |
| Pin 6 | GND — Ground |
| Pin 7 | AIN2+ — Channel 2 differential input positive |
| Pin 8 | AIN2- — Channel 2 differential input negative |
| Pin 9 | GND — Ground |
| Pin 10 | VCM2 — Channel 2 common-mode voltage |
| Pin 11 | GND — Ground |
| Pin 12 | AVDD — 1.8V analog supply |
| Pin 13 | AVDD — 1.8V analog supply |
| Pin 14 | GND — Ground |
| Pin 15 | AVDD — 1.8V analog supply |
| Pin 16 | GND — Ground |
| Pin 17 | SENSE — Internal reference mode select |
| Pin 18 | GND — Ground |
| Pin 19 | REFTOP — Reference top decoupling |
| Pin 20 | REFBOT — Reference bottom decoupling |
| Pin 21 | GND — Ground |
| Pin 22 | REFH — High reference decoupling |
| Pin 23 | REFL — Low reference decoupling |
| Pin 24 | PAR/SER — Parallel/serial configuration select |
| Pin 25 | GAIN — Gain select pin |
| Pin 26 | OVDD — Output driver supply |
| Pin 27 | OVDD — Output driver supply |
| Pin 28 | GND — Ground |
| Pin 29 | CLK+ — Differential clock input positive |
| Pin 30 | CLK- — Differential clock input negative |
| Pin 31 | GND — Ground |
| Pin 32 | ENC+ — Encode input positive |
| Pin 33 | ENC- — Encode input negative |
| Pin 34 | GND — Ground |
| Pin 35 | DA0 — LVDS data output 0 (channel 1) |
| Pin 36 | DA1 — LVDS data output 1 (channel 1) |
| Pin 37 | DA2 — LVDS data output 2 (channel 1) |
| Pin 38 | DA3 — LVDS data output 3 (channel 1) |
| Pin 39 | DA4 — LVDS data output 4 (channel 1) |
| Pin 40 | DA5 — LVDS data output 5 (channel 1) |
| Pin 41 | DA6 — LVDS data output 6 (channel 1) |
| Pin 42 | DB0 — LVDS data output 0 (channel 2) |
| Pin 43 | DB1 — LVDS data output 1 (channel 2) |
| Pin 44 | DB2 — LVDS data output 2 (channel 2) |
| Pin 45 | DB3 — LVDS data output 3 (channel 2) |
| Pin 46 | DB4 — LVDS data output 4 (channel 2) |
| Pin 47 | DB5 — LVDS data output 5 (channel 2) |
| Pin 48 | DB6 — LVDS data output 6 (channel 2) |
| Pin 49 | OVDD — Output driver supply |
| Pin 50 | OVDD — Output driver supply |
| Pin 51 | GND — Ground |
| Pin 52 | FR — Frame output |
| Pin 53 | CLKOUT — Clock output |
| Pin 54 | DCO — Data clock output |
| Pin 55 | OVDD — Output driver supply |
| Pin 56 | GND — Ground |
| Pin 57 | CS — SPI chip select |
| Pin 58 | SCK — SPI serial clock |
| Pin 59 | SDI — SPI serial data in |
| Pin 60 | SDO — SPI serial data out |
| Pin 61 | RESET — Power-on reset |
| Pin 62 | SHDN — Shutdown control |
| Pin 63 | NC — Not connected (per datasheet) |
| Pin 64 | GND — Ground |
Typical Applications
LTC2144IUP-12 is suitable for 6 applications: Cellular Base-Station Receiver Digitizer, Radar and Sonar Signal Chain, Medical Imaging Front-End, Portable Test Instrumentation, Software-Defined Radio (SDR) Platform, Industrial Vibration and Acoustic Monitoring.
Cellular Base-Station Receiver Digitizer
The LTC2144IUP-12's 89 dB SFDR and 0.08 ps RMS aperture jitter let it undersample IF signals from WCDMA and LTE receivers while maintaining spurious-free performance above 80 dB. Its dual simultaneous channels digitize the main and diversity antenna paths from a single IC, eliminating channel-to-channel skew and reducing FPGA capture complexity. The 1.8V analog supply and ~100 mW per channel dissipation make thermal management straightforward in outdoor RRH units.
Recommended
Radar and Sonar Signal Chain
Dual simultaneous-sampling 12-bit channels at 105 Msps let the LTC2144IUP-12 capture I/Q baseband from a radar IF stage with matched gain and phase. The 0.08 ps RMS jitter preserves the noise floor of weak returns, while the 64-QFN exposed pad keeps junction temperature under control during continuous duty cycle. Designers pair it with an FPGA that runs FFT-based Doppler processing on the parallel CMOS or LVDS output data.
Recommended
Medical Imaging Front-End
Ultrasound and other medical imaging systems benefit from the LTC2144IUP-12's matched dual channels and 70.6 dB SNR to capture beamformed I/Q data with low quantization noise. The 64-QFN industrial-temperature grade supports portable cart-top equipment. The 1.8V analog supply plus 1.8-3.3V OVDD simplifies interface to modern low-power FPGAs, eliminating level shifters on the parallel data bus.
Recommended
Portable Test Instrumentation
Handheld spectrum analyzers and oscilloscope front-ends use the LTC2144IUP-12 to digitize two channels of IF data at 105 Msps with low power. Its roughly 100 mW per channel dissipation is acceptable for battery-powered designs, and the dual simultaneous sampling enables phase-coherent multi-channel measurements. The exposed pad of the 64-QFN package provides adequate thermal headroom when stacked under a heat-spreading copper pour.
Recommended
Software-Defined Radio (SDR) Platform
Wideband SDR platforms use the LTC2144IUP-12 to digitize I/Q pairs directly from a quadrature demodulator at sample rates up to 105 Msps. The 12-bit resolution and 70.6 dB SNR support a noise figure adequate for amateur, ISM-band, and light commercial reception. Its CMOS or LVDS parallel output interfaces directly to FPGA DSP fabric for real-time demodulation and decoding.
Recommended
Industrial Vibration and Acoustic Monitoring
Two simultaneous 12-bit channels at 105 Msps allow the LTC2144IUP-12 to capture vibration and acoustic sensor data with exact phase alignment for FFT analysis. The industrial -40C to +85C temperature grade handles factory-floor environments, while the 64-QFN exposed pad simplifies thermal management in sealed enclosures. The on-chip sample-and-hold eliminates external track-and-hold circuits for two-axis accelerometer or microphone arrays.
Recommended
Recommended Products Summary
Engineering reference data for LTC2144IUP-12 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2145IUP-12#PBF | LTC2143IUP-12#PBF | LTC2144CUP-12#PBF | LTC2144IUP-14#PBF | LTC2142IUP-14 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN (UP) 9x9 | 64-QFN (UP) 9x9 - same | 64-QFN (UP) 9x9 - same | 64-QFN (UP) 9x9 - same | 64-QFN (UP) 9x9 - same | 64-QFN (UP) 9x9 - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 14 bits | 14 bits |
| Sample Rate per Channel | 105 Msps | 125 Msps (+19%) | 80 Msps (-24%) | 105 Msps | 105 Msps | 80 Msps (-24%) |
| Number of Channels | 2 simultaneous | 2 simultaneous | 2 simultaneous | 2 simultaneous | 2 simultaneous | 2 simultaneous |
| Operating Temperature Range | -40C to +85C (industrial) | -40C to +85C | -40C to +85C | 0C to +70C (commercial) | -40C to +85C | -40C to +85C |
| Analog Supply (AVDD) | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Output Interface | Parallel CMOS / LVDS | Parallel CMOS / LVDS | Parallel CMOS / LVDS | Parallel CMOS / LVDS | Parallel CMOS / LVDS | Parallel CMOS / LVDS |
Key Differentiators
- Dual simultaneous sampling eliminates channel skew (vs LTC2144IUP-14#PBF)
- Higher speed grade available in same package (vs LTC2143IUP-12#PBF)
- Industrial temperature range for harsh environments (vs LTC2144CUP-12#PBF)
Design Notes
Use a low-noise LDO such as the ADP7104 to generate the 1.8V AVDD rail from a 3.3V or 5V upstream supply. Place a 10 uF X7R ceramic plus a 0.1 uF NP0 ceramic within 2 mm of each AVDD pin; the same goes for the OVDD rail. Separate the analog and digital ground returns and join them only at the exposed pad of the 64-QFN, as recommended in the LTC2145-12/LTC2144-12/LTC2143-12 datasheet.
The 64-QFN (UP) package has an exposed thermal pad (pin 65) on the underside. Estimated: at 105 Msps with both channels active the part dissipates around 200 mW, giving a junction-to-ambient rise of roughly 20 C on a 4-layer board with a 25x25 mm ground pour. For sealed enclosures with limited airflow, expand the thermal copper pour to at least 30x30 mm or add a small heatsink.
Route the differential clock (CLK+/CLK-) and the encode input (ENC+/ENC-) as a 100 ohm differential pair with length matching to within 1 mm. Keep analog input traces (AIN1+/-, AIN2+/-) short and symmetric, and place the AD8138 or equivalent driver within 10 mm of the input pins to preserve the 89 dB SFDR. Avoid routing digital LVDS data outputs over the analog input region of the top layer.
Drive the clock input with a low-jitter source such as the AD9523-1 to take full advantage of the 0.08 ps RMS aperture jitter specification. A 5 ps RMS clock source will degrade SNR by approximately 3 dB at 105 Msps with a 70 MHz input. If the system requires a single-ended clock, AC-couple the unused CLK- input to ground with 0.1 uF.
Do not leave the SENSE pin floating - it selects internal or external voltage reference mode and defaults to internal reference if tied to AVDD. Always assert RESET after power-up and wait at least 1 ms before initiating the first SPI configuration. The exposed pad must be soldered to the ground plane for both electrical grounding and thermal dissipation; an unsoldered pad will trigger thermal shutdown at high ambient temperatures.
Compliance Information
RoHS compliance indicated by #PBF suffix per the DigiKey and Mouser listings. AEC-Q100 not applicable - this is a communications/instrumentation ADC rather than an automotive-qualified part. Halogen-free status not stated in the verified web data.
